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ADC08D1000 - Enable to reach the performance specifications

Sebastien SIFFLET
Prodigy 10 points
Other Parts Discussed in Thread: ADC08D1000

Hello Everybody,

We want to evaluate the performance of the ADC08D1000 but we have some troubles to reach the performance of the device. The component is soldered on  ROGER R007 PCB board. 

The PCB Board is realized in four layers ( include two ground planes), all the decoupling capacitors are closed to the device. three balun ADT2-18 are used for the clock, channel I and channelQ.

All the LVDS output line are matched in lenght and line impedance (50ohms) terminaison (100 Ohms).

All the input Line are matched in lenght and line impedance (50Ohms).

We used LPF 1GHz for the clock and LPF 250MHz for the channels.


Setup of the device

Input: AC Coupled
VCMO=Low

PD=PDQ=Low

Output: DDR
VBG=Floating
Rext=3.3K-0.1%
FSR=High
CalDlyDESSCS_=Floating
OUTV=High
DCLK_RESET=Floating

QUESTION:

When we setup the level for the clock to 600mVpp / 1GHz differential, with no signal in channel Q and Channel I, we have an offset at  the LVDS outputs. Instead having code 127 or 128, we have code 132 or 119.  Can you give us some suggestion to fix the problem?

Thanks for your help.

  • 0
    TI__Mastermind 44350 points

    Hi Sebastian

    If you have  FSR(pin 14)=High you are using the device in Non-ECM (non-extended control mode) with configuration done by pin input only. In this case the CalDly/DES/SCSb pin should not be floating. If it is floating it may prevent a proper calibration from occurring. That may be the cause of what you are seeing. I would recommend setting the CalDly/DES/SCSb pin to logic high to select the longer Calibration Delay setting.

    In case making that change doesn't help, here are a few other things to look at:

    1. I would expect that the output data would toggle between two values that are within a few lsb of each other. If the output is changing only in larger steps I would make sure that all bits received by the FPGA are toggling. You could try applying an input signal that is close to full scale to see if some bits captured at the FPGA are always stuck at 0 or 1.
    2. Have you observed this on multiple boards, or have you only tested a single board so far?
    3. Is the device power consumption within the expected range listed in the datasheet?
    4. Once the part is powered up, if you initiate a calibration using the CAL input pin does the output code get closer to the expected values? Please confirm the calibration process is running by monitoring the CalRun output.

    If possible please attached your ADC related schematics in .pdf format.

    Best regards,

    Jim B