Hi,
I am trying to interface the ADS62P43 EVM board with a Virtex-5 FPGA board from Xilinx. I have currently connected the two boards together. A 20 MHz clock source is provided to the ADS62P43 EVM board by a 100 MHz oscillator in the FPGA board. I am using a DCM to divide the 100 MHz clock to supply a 20 MHz clock source to the ADS62P43 EVM board ( via SMA connectors). I have connected the data lines together using CMOS interface. I have programmed a VHDl code onto the FPGA board where all the data lines are buffered and also the clock output. I have also set the ADS62P43EVM board with default register settings. But when I run the two boards, I am not able to get a clock output from the ADS62P43. In order to make sure my clock source is correct, I detected the clock on an oscilloscope and it clearly shows a square wave being fed to the ADS62P43 board. I am not sure what the problem is? If anyone is aware of what the problem could be, please let me know.. I am not sure If I am following the correct procedure.
Thanks
Mahadevan