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DAC7562T minimum rise/fall times

Dan Andersen
Genius 11390 points
Other Parts Discussed in Thread: DAC7562T

Is there a max/min spec for the rise and fall times of the input clock on the DAC7562T?  My customer would like to run this as slowly as possible to reduce EMI..  Any other caveats here?

Thanks,

Dan

  • 0
    TI__Mastermind 46290 points
    Dan,

    There may be some impractically fast rise/fall time that would break the interface but I don't think there is any point where the rise/fall times would be too slow for the device to recognize. In the end the interface is looking for specific logic thresholds in the rise/fall of the SCLK signal in order to determine when to latch data. If the interface is slow it should be, if anything, better or more reliable at catching edges.

    Our DACs often have digital feed-through specifications, for customers that are particularly conscious of digital feed-through (basically just a specific form of EMI) we've placed R/C filters in the digital lines for exactly this purpose of slowing the rise/fall times to help make sure the high-frequency content associated with the digital signals doesn't capacitively couple (either via device or via PCB) to the output.

    I will still double-check for you whether it's possible to be too slow.