SYNC lock issue with ADC12J4000 with KC-705

deepak kumar32

Other Parts Discussed in Thread: ADC12J4000, LMK04828, TRF3765, ADC12J4000EVM

Hello,

I am trying to lock SERDES between ADC12J4000 EVM and KC-705. I am using Decimation bypass mode. I can get the Refclock, and core clock in KC-705. The JESD interface of KC-705 is set to 4 Gsps with QPLL at 200 MHz.

Following is register dump of JESD:

-------------------------------------
-- RX register Dump                --
-------------------------------------
RX_VERSION_REG      0x07000000
RX_RESET_REG        0x00010000
RX_ILA_SUP_REG      0x00000001
RX_ILA_SUP_REG      0x00000001
RX_SCRAMBL_REG      0x00000000
RX_SYSREF_CTRL_REG 0x00000000
RX_TEST_MODE_REG    0x00000000
RX_ERROR_STAT_REG0 0x00000000
RX_F_REG            0x00000001
RX_K_REG            0x0000000F
RX_LANES_REG        0x000000FF
RX_SUBCLASS_REG     0x00000001
RX_RX_BUF_DELAY_REG 0x00000000
RX_ERR_REP_REG      0x44A10034 0x00000001
RX_SYNC_STAT_REG    0x44A10038 0x00010000
RX_ERROR_STAT_REG1 0x44A1003C 0x00000000
-------------------------------------

I am using following config files for EVM for configuration:

LMK04828_DB1_Fs_3500Msps.cfg
ADC12J4000_DB1_DDR.cfg
TRF3765_Fs_4000Msps.cfg

Additionally, I changed the following registers in ADC12J400:

0x0201 0x3F // Scrambler off, KM1 = 16, DDR, JESD enabled
0x0210 0x48 // NCO_F0A (for 4Gsps)
0x0211 0x66 // NCO_F0B(for 4Gsps)
0x0212 0xCE // NCO_F0C(for 4Gsps)
0x0214 0x22 // NCO_F0D(for 4Gsps)

The 0x100, 0x110 and 0x130 registers of LMK4828 were changed to 0x10 with 0x137 changed to 0x1.

I am not sure what else I am missing?

I am now trying to emulate the setup as in post shown below, i.e. 1Gsps with ADC sampling freq at 4GHz and decimation by 4 and 10 to get it down to 1 Gsps and 400 Msps. My question is whether I have to keep 1Gsps and 4Msps for my FPGA configuration? I will keep QPLL of receiver of FPGA to be using 200 MHz.

e2e.ti.com/.../1964075

Thanks,

over 9 years ago

0 jim s over 9 years ago

TI__Guru* 91947 points

If you are using bypass mode, this requires 8 Serdes lanes. The KC705 only has 4 lanes routed. This mode is not supported by the KC705. You will have to use a decimate mode. See attached example.

Regards,

Jim

KC705_Dec_4.pptx

0 deepak kumar32 over 9 years ago in reply to jim s

Intellectual 350 points

Jim,

Thanks for your response. Can you answer following questions:
1] Only GUI ver A is available in EVM package and not ver 1.3 as in doc specified. I do not see delay parameter in Jesd tab. Is it required to be changed?
2] If only 4 lanes can be used, I will go with 1 Gsps first. Can you suggest which config files should I use ?
3] Should KC-705 JESD interface be set for 1 Gsps with refclk and coreclk set based on 1 Gsps/5 = 200 MHz ?

Thanks,
D

0 jim s over 9 years ago in reply to deepak kumar32

TI__Guru* 91947 points

What is the revision on your ADC12J4000EVM? If you tested this with a TSW14J56EVM by any chance?

Jim

0 deepak kumar32 over 9 years ago in reply to jim s

Intellectual 350 points

The board says ADC12JxxxxEVM A. I have not tested it with TSW14J56EVM.

For a case of 3.5Gsps with DDR and with no Decimation , (as in the link provided by you), should I keep the lane rate at 5.25 Gbps ?

Following is extracted from config decision table:
Bypass Onboard 3500 3500 LMK04828_DB1_Fs_3500Msps.cfg TRF3765_Fs_3500Msps.cfg ADC12J4000_DB1_DDR.cfg

D

0 Tuan Truong46 over 9 years ago in reply to deepak kumar32

Prodigy 110 points

Hi deepak,
According to my calculation (and measured valued) in DEC_4 DDR P54 configuration the linerate is 10 Gbps, the refclk is 500 MHz (line rate / 20) and the coreclk is 250 MHz.
I'm using their HDL design version 2.8 and ADC12J4000EVM GUI A. All I have to change is the value of register 0x110 of the LMK04828. You should devide the value by two (to double the clock frequency so that the 250 MHz default value becomes 500 MHz). As far as I know this clock (500 MHz) is also the reference clock for the QPLLs.
Hope this helps.

BR,
Tuan

0 deepak kumar32 over 9 years ago in reply to Tuan Truong46

Intellectual 350 points

I used ADC12J4000_DB1_DDR.cfg with Fs=3500. It is working fine now. You are right that we have to change LMK04828 reg 0x110 by half.

Kudos to your prompt response.

0 jim s over 9 years ago in reply to deepak kumar32

TI__Guru* 91947 points

When sampling the ADC at 3.1Gsps and using dec 4x mode, the lane rate will be 8.75Gbps. The Serdes in the KC705 has a dead spot between 8-9.8Gbps. You will need to either lower or raise your sample rate to get out of this range. I have also attached an updated version of the TSW14J10EVM User's Guide. See section 6 for how to determine the required FPGA reference and core clocks. I have also attached an example using the ADC12J4000 with the KC705 and how to program the LMK04828 properly for this interface.

Regards,

Jim

TSW14J10EVM User's Guide.pdf

ADC12J4000_DEC_4_P54_KC105.pptx

0 Tuan Truong46 over 9 years ago in reply to jim s

Prodigy 110 points

Hi Jim,
Can you tell me in which document they say the KC705 SERDES has a dead spot between 8-9.8 Gbps?
Thanks.

BR,
Tuan

0 deepak kumar32 over 9 years ago in reply to jim s

Intellectual 350 points

Jim,

For your case,

Fs = 3500
Decimation = 4
ADC bits = 16
With 8/10 encoding bit loading = 1.25
lane s = 4

Thus Lane rate = (3500/4) *(16*1.25)/(4/2) = 8.75

With my required case:
Fs = 3500
Decimation = 1
ADC bits = 12
With 8/10 encoding bit loading = 1.25
lane s = 8
=> Lane rate = (3500/1) *(12*1.25)/(8/2) = 13.125

Does it mean that I will not be able to get that Fs even with 8 lanes as 13.125 Gbps lane rate will be over kill for Kintex?

Thanks,
D

0 jim s over 9 years ago in reply to deepak kumar32

TI__Guru* 91947 points

Yes, and you cannot run in dec 1 mode. This requires 8 lanes and the KC705 only routed 4.

Jim

0 deepak kumar32 over 9 years ago in reply to jim s

Intellectual 350 points

I meant if I chose a board that has 8 lanes based on Kintex-7 device. I understand 4 lane limitations of KC-705.

D

0 Jim Brinkhurst1 over 9 years ago in reply to deepak kumar32

TI__Mastermind 44680 points

Hi Deepak

The lane rate calculation for Decimate by 1, raw 12 bit mode is as follows. The rate is lower because we use efficient packing of the 12 bit data into the octets in the frame, with only 4 tail bits needed to file up a frame that is 8 octets long. (See Tables 12 and 13 of the ADC12J4000 datasheet).

Lane Rate = (ADC_Sample_Rate * N' * (10/8) * (16/15)) / Lanes

For your case this gives: (3500MSPS * 12 *(10/8) * (16/15)) / 8 = 7000 Mbit/sec.

Best regards,

Jim B

0 deepak kumar32 over 9 years ago in reply to Jim Brinkhurst1

Intellectual 350 points

Jim,

Thanks a lot for explanation.

D

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SYNC lock issue with ADC12J4000 with KC-705