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Hi,
I received the following question from my customer.
Could you tell me input capacitance and equivalent circuit and of CLKIN?
They are evaluating ADS5401, and the LMK04131 provides CLK by PECL.
However the CLK can not be observed when CLK is higher than 750MHz.
(It can be observed when CLK is lower frequency for example 400MHz.)
DACLK can be observed 400MHz signal on this condition.
They think that it causes by wrong impedance matching.
So they need information of title.
And please let me know information to solve this problem.
Please let me know if there is lack of information.
Best Regards,
Kuramochi
Hi,
I have asked the design manager for an equivalent input circuit for the clock input of the device. We sometimes have such an equivalent circuit listed in the datasheet but for this device we did not. I suspect that internal loading on the clock input may be making it harder to drive a larger input swing at the higher sample rates, although I haven't seen it on my EVM, perhaps due to my using a 50 ohm signal source that is able to drive the signal. If capacitive loading on the signal is an issue, what I have seen done on other devices is to use an L-C matching circuit external to the clock input. An example of this is described in the application note http://www.ti.com/lit/an/slyt679/slyt679.pdf . But in order to try this same approach with the ADS5401 we would need to have the s parameters of the clock input or at least an equivalent circuit of the clock input, so I have asked for this.
Regards,
Richard P.
Hi Richard-san,
I would like to confirm additionally.
You said that " I haven't seen it on my EVM".
Is this the condition using the LMK04131?
Please let me know if there is lack of information.
Regards,
Kuramochi
Kuramochi,
I am covering for Richard while he is on vacation. I looked at the ADS5401EVM and the clock input is coming from an external signal generator through a transformer. There is no LMK04131 in the path.
Regards,
Jim
Jim-san,
Thank you for your answer.
Is it difficult to get the input capacitance and/or equivalent circuit and of CLKIN?
Best Regards,
Kuramochi
Kuramochi-san,
I have requested the input capacitance information from the design team. The equivalent circuit is shown below.
Regards,
Jim
Also, I don't know if this has been communicated yet but the design team reports the parasitic capacitance to be
around 1.4pF on each node, CLKINP, and CLKINM.
Regards,
Richard P.