DAC5688 using PLL clock mode, problem in loss of PLL lock

bo li77

Other Parts Discussed in Thread: DAC5688, DAC5687, DAC5686

Dear all,

the pll clock mode of dac is used. This SE-clock from the clock distributor is inputted to the pll of DAC5688. The output of the pll will be used as the internal clock of DAC. However, the pll is always lose of lock after I configurate this dac SIF registers.

Serial interface between FPGA and DAC works fine. I checked again the clock input, power supply and reset input. They all looks fine. Now I have no idea about why this pll dose not work.

Any suggestion will be appreciated!

Configuration used:

CONFIG1 0x01 0x08

CONFIG2 0x02 0x40

over 7 years ago

0 Neeraj Gill over 7 years ago

TI__Mastermind 20541 points

Hi Bo li77,

To use the PLL you will need to provide differential clock signal to the CLK2/C input pins. You will have to enable PLL with config26 PLL_ena. Set the PLL N and M divider using config 29. Can you please tell me you input clock reference frequency, DAC sample rate and interpolation I will try to replicate your setup in lab.

Regards,

Neeraj Gill

0 bo li77 over 7 years ago in reply to Neeraj Gill

Prodigy 30 points

Hello Neeraj Gill,

Thanks for you reply. I use the clock distributor AD9513 to generate 1 pair differential clock to input to CLK2/C and one single-end clock to input to CLK1. PLL_ena is enabled, beccause of the default sif registers setting. In my project I used 250MHz and I notice that the maximum operating frequency of PFD is 160MHz. So try using 100MHz and 250Mhz with the PLL_N = 2 and PLL_M =2.

Clock reference frequency : 100MHz or 250MHz

DAC sample rate : 100MHz or 250MHz

interpolation

: 1

Here is a list of my test you may be want to know

-CLKVDD   1.773V
-IOVDD    3.290V
-DVDD_1   1.779V
-DVDD     1.776V
-AVDD     3.250V

-DAC_RESET HIGH(3.217V) before it goes high, the RESETB pin active low for
longer than 25ns pulse width

-DAC_TXEN goes HIGH(3.221V) after the power, clock and configuration

-DAC_EXTIO open

-DAC_EXTLO to GND

-DAC_SDENB gose LOW when the serial interface is working

Besides that, I also have one question. I take this dac design from other people.
However, I can not understand what is the usage of clk1 when it is set to be the input of dac in the PLL CLock Mode.
Because I see from the datasheet of dac5688 the input of internal PLL is always CLK2/C.

I also check the PLL Clock Mode of DAC5686/DAC5687. 
Please find the file in this link. www.ti.com/.../slwa040a.pdf
In DAC5686/DAC5687, if the Clk1 is set to be the input of DAC, the internal clock which is generated from internal PLL has nothing to do with CLK2/C. 
CLK1 is the reference clock of this internal PLL.

Is this the same situation happens in the dac5688?

Thanks for you reply again. Please help me.

Best Regards

0 bo li77 over 7 years ago in reply to Neeraj Gill

Prodigy 30 points

Hello Neeraj Gill,

Thanks for you reply. I use the clock distributor AD9513 to generate 1 pair differential clock to input to CLK2/C and one single-end clock to input to CLK1. PLL_ena is enabled, beccause of the default sif registers setting. In my project I used 250MHz and I notice that the maximum operating frequency of PFD is 160MHz. So try using 100MHz and 250Mhz with the PLL_N = 2 and PLL_M =2.

Clock reference frequency : 100MHz or 250MHz
DAC sample rate : 100MHz or 250MHz

interpolation
: 1

Here is a list of my test you may be want to know

-CLKVDD 1.773V
-IOVDD 3.290V
-DVDD_1 1.779V
-DVDD 1.776V
-AVDD 3.250V

-DAC_RESET HIGH(3.217V) before it goes high, the RESETB pin active low for
longer than 25ns pulse width

-DAC_TXEN goes HIGH(3.221V) after the power, clock and configuration

-DAC_EXTIO open

-DAC_EXTLO to GND

-DAC_SDENB gose LOW when the serial interface is working

Besides that, I also have one question. I take this dac design from other people.
However, I can not understand what is the usage of clk1 when it is set to be the input of dac in the PLL CLock Mode.
Because I see from the datasheet of dac5688 the input of internal PLL is always CLK2/C.

I also check the PLL Clock Mode of DAC5686/DAC5687.
Please find the file in this link. www.ti.com/.../slwa040a.pdf
In DAC5686/DAC5687, if the Clk1 is set to be the input of DAC, the internal clock which is generated from internal PLL has nothing to do with CLK2/C.
CLK1 is the reference clock of this internal PLL.

Is this the same situation happens in the dac5688?

Thanks for you reply again. Please help me.

Best Regards

0 Neeraj Gill over 7 years ago in reply to bo li77

TI__Mastermind 20541 points

Hi bo li77,

PLL in the DAC is generally used to generate higher frequency clock to drive the DAC sampling clk when high frequency clock is not available. As far as I could understand from your description, it sounds like your you have 100MHz clock or 250MHz reference clock and you are using PLL to generate 100 or 250MHz DAC sampling clk by using M =2 and N=2 for PLL M/N ratio. That being said I don't understand why you want to use PLL in the DAC to generate same frequency provided to the PLL? As far as I could tell PLL would degrade the output performance compared to the CLK buffer chip that you are using.

However I am attaching the register values I have for my setup. In my setup I am using 250MHz Reference signal feeding into the CLK2/CLKC2 input and using PLL of DAC to generate 250MHz signal(same as you are doing). I am using constant input data and NCO to generate the signal at 30MHz. You can check the status of PLL_lock by CONFIG0 BIT 7, If it is asserted the PLL is locked.

Regards,

Neeraj Gill

DAC5688 250 constant data NCO 30

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DAC5688 using PLL clock mode, problem in loss of PLL lock