ADS62P43 clock inputs

Hi,

Please see the answer under the questions,

We have a ADS62P43 and are attempting to interface it with a Xilinx FPGA development board over a 136-pin Samtec connector.  Can we drive the ADC clock (CLKP/CLKM) using a differential clock output from the FPGA over a ribbon cable?

    Yes, at the device speed if you keep the length of ribbon cable short as possible (less than 3" is my experiance for your reference). But jitter/noise on the clock should be small inorder to keep good performance. 

What is the appropriate clock input voltage?

    The clock input voltage spec is shown in the spect table in the data sheet, page 4.

We have access to 3.3 V and 2.5 V. If these voltages are not appropriate, can an RLC network be added to our PCB to obtain the appropriate voltage?

    You can add a RLC, but it may not need, differential 3.3v or 2.5v sine wave is in the spec range. But it needs to avoid over spec range (see max rating table in page 3.), please spply the voltage about the typ value of the spec.

If the above scenario is not feasible, can we use a CMOS clock source for CLKP/CLKM (as shown on page 47 of the ADS62P43 manual) with LVDS data output?

   Yes, you can.  Since SE CMOS clock is in the spec range and output data mode setting is not relative to the clock type.  

Regards,

Hui Qing