Other Parts Discussed in Thread: REF5025
Hi
I am using the ADS1298 and I am struggling to get a consistent test signal amplitude. The Test signal amplitude varies depending on the number of channels enabled. Is this correct?
My set up is as follows:
- I have 4 ADS1298 operating in multiple read back mode. The first ADS1298 supplies the clock signal to the other 3.
- Reference voltage is external, 2.5V (REF5025, using suggested circuit in data sheet)
- AVDD and DVDD: Supply voltage 3.1V.
The gain has been set to 6 (default), so I am expecting a Test voltage amplitude of +-1.04mV. (2.5/2400 V). I am able to measure this on the first ADC only when one channel is enabled. If all 8 channels are enabled, I measure 1.4mVp-p. This behaviour varies across all four ADS1298. On the second ADS1298, I measure the expected voltage when all 8 channels are enabled.
The registers (for the first ADC) are as follows (ADC 2-4s have Config 1 = 0x46, Config 3 = 0x40) :
The Raw ADC data for Channels 1 (blue trace), 9 (pink), 17 (green) and 25 (red) (I.E. Ch 1 of each ADS1298 chip) is shown below. Ignoring the offset, you will notice each channel has a different peak-peak amplitude.
The graph below shows the ADC data when only Channel 1 of ADC 1 is enabled and the remaining 7 channels are powered down (Bit 7 of CHnSET set). The remaining 3 ADCS still have all channels enabled.
You will notice that the blue trace (Channel 1) now has a maximum ADC value of ~ 5616, instead of ~3700 as shown in the previous graph. The only difference in the set up is Channels 2-8 are powered down.
Can anyone offer any insight into this issue?
Thank you for your help.
kind regards,
Geoff