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DAC5688: Question about the case of CLK2 only use

Guru 18595 points
Part Number: DAC5688
Other Parts Discussed in Thread: ADS4146, CDCM7005

Please let me know about the case of CLK2 only use below,

①About configuration for CLK2 only use, is attached file correct?

 If there adjusting point, please let me know


②Is there described the CLK2 only use on the datasheet or any document?


・Customer is evaluating, but DAC5688 is not output.

 They are checking way of measure, one of idea is CLK2 only use.

・DAC5688 Input is ADS4146 for default. 

・Customer is tried EXTERNAL CLOCK MODE, but DAC5688 is not output, too. 

・Other setting is below,

 ・fir4_ena: FIR4 Inverse SINC filter

 ・diffclk_ena: Differential CLK1

 ・sif_sync_sig: Sync SIF

 ・mixer_gain: MIXER +6dB

 ・nco_reg_sel(1:0): Choice the TXENABLE from FIFO output for Sync signal NCO register

 ・io_1p8_3p3: 1.8V

 ・PLL_sleep: PLL sleep

 ・PLL_ena: PLL disable


Best regards,


  • Hi Satoshi,

    Table 5 on page 33 of the datasheet explains how to setup registers for various clock modes. In mean time I will try to go through the register setting you have sent me and get back to you.

    Neeraj Gill
  • Hi Satoshi,

    I have created a file which enable contant data and uses NCO to generate 89.1MHz signal. All you need to do is provide 654.4 MHz clock signal to CLK2 of DAC and load the file to setup the DAC and it should output 89.1MHz signal output. Once this file is loaded to the DAC you can also change change the clock rate and setup NCO generate your required frequency signal. This flle is created from DAC5688 GUI software so at the bottom it also has CDCM7005 register setting if you not using the DAC EVM and GUI you can discard those register values. This is a text file you can open it in notepad if you want to look at it.


    Neeraj Gill

    DAC5688 654p4 constant data NCO 89p1

  • Neeraj Gill-san

    Thank you for kind support.

    Sorry for addition, can you accept two points request below?
    ①CLK2 only use setting on EXTERNAL CLOCK MODE.
     For example; synchr_clkin, clk1_in_en, diffclk_ena, PLL_ena are all zero setting. (by Datasheet Table 5)
    ②If I send customer DAC5688 schematic to you, do you create to conforming with customer schematic?

    Best regards,
  • Hi Satoshi,

    Sorry for late reply. I was on vacation last week and came back to work today. Yes please send me the customer schematic I can take a look at it.

    Neeraj Gill