TLV5636: DAC register write immediately following a Reference Select write

Hi Scott,

Thank you for your query. I am assuming that you have tested the system with only one write after the control write. If so, then could you please send a scope capture of the waveforms?

Regards,
Uttam Sahu
Applications Engineer, Precision DACs

Hello Uttam,

First an update: the problem now persists for any type of write (CONTROL and DAC). It is not limited to a DAC write after a control write.

In order for the hardware to function properly every time, I am forced to repeat all writes. The problem is intermittent, that is to say that single writes do work on occasion. That leads me to believe that it is a setup problem or perhaps related to the re-use of SOMI as the FRAME SYNC pin on the TLV5636.

Second: lets make sure the SPI peripheral (MSP432) is configured properly for interfacing with the TLV5636.

SPI initialization:

// SPI Master Configuration Parameter

const eUSCI_SPI_MasterConfig spiB2_Config =

{

EUSCI_B_SPI_CLOCKSOURCE_SMCLK, // 12MHz SMCLK Clock Source

12000000, // SMCLK = 12MHZ

12000000, // SPICLK = 12MHZ -> for TLV56XX DACs

EUSCI_B_SPI_MSB_FIRST, // MSB First

EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT, // Phase

EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW, // Low polarity

EUSCI_B_SPI_3PIN // 3Wire SPI Mode: SOMI, SIMO, CLK: Note that SOMI is later configured as GPIO for use as the DAC Frame Sync

};

//============================================================

// Description:

//

// It is assumed that clocks have

// been previously configured.

//

// If successful, return TRUE, otherwise FALSE

//============================================================

BOOL BP2_Slave_Transmitter_SPI_B2_Init(void)

{

BOOL bReturnVal;

bReturnVal = RSC_TRUE;

//============================================================

// Specific to the MSP432P401R Launch Pad Development Platform

//============================================================

//========================================================

// Configuring EUSCI_B2_SPI pins and GPIO pins for used with EUSCI_B2_SPI interface

//========================================================

// P3.5: SPI_B2 -> CLK

MAP_GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P3, GPIO_PIN5, GPIO_PRIMARY_MODULE_FUNCTION);

// P3.6: SPI_B2 <- SIMO

MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P3, GPIO_PIN6, GPIO_PRIMARY_MODULE_FUNCTION);

//========================================================

// Configuring SPI_B2 in 3wire master mode

//========================================================

bReturnVal &= MAP_SPI_initMaster(EUSCI_B2_BASE, &spiB2_Config);

// P3.7: Host MCU output -> DAC Frame Sync

MAP_GPIO_setAsOutputPin(GPIO_PORT_P3, FSYNC_GPIO_BIT);

// P5.5: SPI_B2 -> Chip select

MAP_GPIO_setAsOutputPin(GPIO_PORT_P5, B2_SPI_CS_BIT);

B2_SPI_DEASSERT_CS();

B2_SPI_DEASSERT_FS();

//========================================================

// Enable SPI_B2 module

//========================================================

MAP_SPI_enableModule(EUSCI_B2_BASE);

MAP_SPI_clearInterruptFlag(EUSCI_B2_BASE, (EUSCI_SPI_RECEIVE_INTERRUPT | EUSCI_SPI_TRANSMIT_INTERRUPT));

MAP_SPI_disableInterrupt(EUSCI_B2_BASE, (EUSCI_SPI_RECEIVE_INTERRUPT | EUSCI_SPI_TRANSMIT_INTERRUPT));

return bReturnVal;

}

Hi Scott,

As you pointed out the CS signal can be a problem. Your code seems ok. Usually these type of problems occur due to setup/hold timing related issues or due to signal integrity level issues. Hence, it will be a good idea to look at the waveforms. Could you please attach a scope capture?

Regards,
Uttam

Top line (yellow) = SPI SIMO

Next line (green) = SPI CLK

Next line (blue) = SPI CS

Next line (red) = DAC Frame Sync

At 1usec per time division, all setup and hold timing requirements are met

Hi Scott,

The high-level waveform looks fine. Is it possible for you to zoom-in the clock and data lines and attach. This will let us know whether anything is on the edge or not.

Another doubt - are your signal levels 3.3V or close to 2.5V. I am not able to clearly make out from the waveform. As the VIH is 2.4V for 5V VDD, I want to make sure we are not violating this condition anywhere.

Regards,
Uttam

Zoom view of data lines.

MSP432 is operating from 3v

TLV5636 is operating from 5.5V

MSP432 SPI lines that must meet Vh-in on the TLV5636 reach > 2.8V.

Further evidence. 2 series of scope captures: one for the TLV5606 (10bit DAC) and one for the TLV5636 (12bit DAC).

The host MCU is an MSP432 operating from 3.0V. The DAC power supply is 3.6V in BOTH cases. All DAC signal lines exceed 2.8V logic high. Both cases show that ONLY EVERY OTHER DAC write results in a change in the DAC output. DAC update rate is 100kHz. The FAST BIT is set for each DAC data write.

Scope Capture decoding:

Channel 1 (yellow) is SPI master data out

Channel 2 (green) is the SPI master clock

Channel 3 (blue) is TLV56xx DAC frame sync

Channel 4 (red) is the DAC output.

TLV5606 series:

DAC write sequence:

0x44FC - output changes
0x46F8 - output does NOT change
0x48F4 - output changes
0x4AF0 - output does NOT change

0x44FC is written and the output changes.

0x46F8 is written and there is NO change in the DAC output.

TLV5636 series:

DAC write sequence:

0x44FF - output changes
0x46FE - output does NOT change
0x48FD - output changes
0x4AFC - output does NOT change

0x44FF is written to the DAC and the output changes.

0x46FE is written to the DAC and there is no change in the OUTPUT.

I this point it appears as though there is something is inherently incompatible between the MSP432 SPI peripheral and TLV56xx series DACs.

Please advise as it is critical that I get a high speed, fast settling DAC to interface with the MSP432 SPI peripheral.

To TI,

Please acknowledge my last post!

Hi Scott,

Sorry for delay. I was a bit caught up in few things. I am currently looking into your waveforms. Will get back soon.

Regards,
Uttam

Apparently the MSP432 SPI Peripheral must be set for:

// SPI Master Configuration Parameter
const eUSCI_SPI_MasterConfig spiB2_Config =
{
EUSCI_B_SPI_CLOCKSOURCE_SMCLK
12000000
12000000
EUSCI_B_SPI_MSB_FIRST
EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH, // Doesn't make sense but TLV56xx parts need this setting
//EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
EUSCI_B_SPI_3PIN // 3Wire SPI Mode: SOMI, SIMO, CLK
};

Things are working now.

Thanks