ADS61B29: ADC FPGA Interface verification

Hi,

The schematics look good to me.  it looks like you mostly copied the EVM for the analog input, which is fine, with the exception of using the TC1-1-13 balun which is also fine.  On our EVM we chose to not install the termination resistors between the transformers and have two 25 ohm termination resistors after.  you chose to have 100 ohms between the baluns in parallel with 100 ohm after, for a net effective of 50 ohm termination.  This is fine also - that is why it was one of the options on the EVM. 

individual supplies for each ADC should help keep them isolated which is good. 

regarding the ADCs being synchronized - if they are all clocked at the same time then the samples present at the ADC outputs should all be present at the same time as the latency through the ADCs would be the same for all devices.   the only timing difference from one ADC to another would be the min to max spread of aperture delay between one device and another as shown in the specification at the top of page 10 of the datasheet.   Aperture delay is the amount of time from when the clock edge is present at the input pins until the actual sample is taken - and there is some device to device variation in that value.   The min to max spread of aperture jitter is across the full range of temperature and voltage, so if all six devices are at nearly the same temperature and nearly the same voltage then this device to device variation would me much smaller.  (it would be very unusual for a device to be at -40C while another device an inch away was at 85C for example.)

Regards,

Richard P.

Hi RIchard,

Thanks for the review. Your reply is so helpful to proceed further with the design.
We will take care to keep all ADC in same temperature and voltage.

Can you please review the clock section also. Because synchronization of the 6 ADCs are so critical in our application.

Regards

Athuljith

hi,

the clock chip you show is not a TI device so we would not be able to review that.   But I see that the clocks are AC coupled so that the ADCs can bias the signals to the desired level, so you would just need to make sure that the clock routing to each ADC is matched lengths to ensure that the clock signals get to each ADC at the same time. 

for the FPGA interface, you would need to use the LVDS DDR clock from each ADC to latch the DDR data from that ADC into the FPGA.  so you would want to be sure that each of the clocks from the six ADCs all go to clock-capable inputs in the FPGA.  Depending on the sample rate you would be using, the setup and hold time for the data around the clock edges of the clock from that ADC can be pretty tight, so you would have to check timing closure into the FPGA for the data around the clock edges for each of the ADCs.     Then once you have the data from each ADC safely latched into the FPGA using the six individual clocks, you would probably wish to relatch the data from the individual ADCs onto a single clock to process the data all on one clock domain, whatever it is you wish to do with the data in the FPGA.  you would need to work with your FPGA support on timing closure and whether you have enough clock capable inputs.

Regards,

Richard P,