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I'm designing a new board with ADS4249 connected to Xilinx FPGA.
The FPGA is sending the clock to the ADS4249 and there is an input fo rthe clock produced by the ADS4249 for sampling the output data.
I noticed that you added a CDCE72010 clock stabilizer in the ADS4249 evaluation board. It is necessary for an application where the sampling clock is produced by an internal PLL inside teh FPGA?
What are the criteria for using that clock stabilizer?
Hi Aronii,
Looking at the EVM design schematic (located here www.ti.com/.../ads42b49evm Documents), the CDC was mainly placed on the EVM to allow for the option of internal clocking (see also the optional onboard oscillator) by way of the CDC PLL. The clock input and analog input do not touch the CDC by default on the EVM.
Best regards,
Dan
