Other Parts Discussed in Thread: CDCE72010
I'm designing a new board with ADS4249 connected to Xilinx FPGA.
The FPGA is sending the clock to the ADS4249 and there is an input fo rthe clock produced by the ADS4249 for sampling the output data.
I noticed that you added a CDCE72010 clock stabilizer in the ADS4249 evaluation board. It is necessary for an application where the sampling clock is produced by an internal PLL inside teh FPGA?
What are the criteria for using that clock stabilizer?
