Hi,
- According to a post I found here here:
"The fusefarm contains an internal prom that is used to load certain registers after a hard reset is issued after power has been stabilized. This must be done every time the DAC is turned on". - In our design, AUTOLOAD_DONE field is not set (=0) and EFC_ERR = 00000 (Vendor ID and Chip Version Register (address = 0x7F)).
- We are following the sequence in figure 141:
TXENABLE low. All voltages are ok. TRSTB low. DACCLKSE input is provided (9GHz / 1Vpp sine wave via DC block capacitor). RESETB goes low and high.
In this sequence we also program the device to 4-wire and setting SEL_EXTCLK_DIFFSE=1 (and repeat these two after each RESETB toggle).
- What are we doing wrong that AUTOLOAD_DONE is not set?
How come it is not set while EFC_ERR = 00000? (no errors from the fuse farm) - When Autoload sequence is not done, will it block me from programming certain registers? Or outputting, for example, a divided DAC CLK to CLKTXP/N?
I was unable to read successfuly what I programmed into Divided Output Clock Configuration Register (address = 0x0C) and Clock Input and PLL Configuration Register (address = 0x31).
Thank you
Gil
