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DAC8775: data register reads back zero

jgla
Prodigy 60 points
Part Number: DAC8775
Other Parts Discussed in Thread: DAC8760, DAC8551

Are there any special preconditions before writing to the DAC8775 DAC data register (address 0x5) other than selecting it?  Regardless of the value I write, it reads back as zero.  Any other registers read back the same as written (with the exception of, e.g., the reset register's RST bit).
Here is some pseudo code and the values read back:

  call anlg_out1_reset
    - toggle DAC \reset pin low for 62us, then high 
    - call spi_write_3bytes(0x01, 0x00, 0x01) ;  // software reset
  call anlg_out1_configure ;

  call anlg_out1_readback_reset_config_register  ; // 0x82 1e 02 
  call anlg_out1_readback_status_register        ; // 0x8b 17 80
  call anlg_out1_bb_select_a
  call anlg_out1_readback_bb_select_register     ; // 0x86 00 01 
  call anlg_out1_readback_bb_config_register     ; // 0x87 02 1f 
  call anlg_out1_dac_select_a
  call anlg_out1_readback_dac_select_register    ; // 0x83 00 20
  call anlg_out1_readback_dac_config_register    ; // 0x84 90 00
  call anlg_out1_readback_cal_enable_register    ; // 0x88 00 00
  call anlg_out1_readback_gain_register          ; // 0x89 80 00
  call anlg_out1_readback_zero_register          ; // 0x9a 00 00
  call anlg_out1_readback_dac_config_register    ; // 0x84 90 00
  call anlg_out1_dac_data(0x4001)  ; // write 0x4001 to DAC A
  call anlg_out1_readback_data_register          ; // 0x85 00 00
  call anlg_out1_dac_data(0xc002); // write 0xc002 to DAC A
  call anlg_out1_readback_data_register          ; // 0x85 00 00

Any suggestions?

BTW, I also tried configuring the DAC output, then enabling it in two steps, per this post
  https://e2e.ti.com/support/data_converters/precision_data_converters/f/73/p/633490/2338051?tisearch=e2e-sitesearch
without any change in the result.

Thanks.
Joe

  • 0
    TI__Expert 5820 points

    Hi Joe,

    No, there are no specific preconditions required to write to the DAC data register. What is the status of the CLR pin and the status of the LDAC pin? If CLR is accidentally tied high then all of the DAC outputs will be reset. Additionally, the LDAC pin should be set low for asynchronous operation.

    I am unable to verify the actual SPI data sent by your functions without seeing the waveform capture. Can you provide a capture of the SPI waveforms for the 'anlg_out1_dac_data'? There may be an issue with this function or 'anlg_out1_readback_data_register' where the SPI transfer is incorrect. The best way to verify is by capturing the waveforms SCLK, SDIN, SDO, and SYNC on one scope capture.

    Thanks,

    Garrett

  • 0 in reply to Garrett Satterfield
    Prodigy 60 points

    Hello Garrett:
    I will capture some SPI data shortly.
    The CLR pin is grounded.

    At the moment, the SPI sequence is:
      LDAC low
        (>100ns elapses)
      SYNC low
      write 3 bytes to SPI
      SYNC high
       (>100ns elapses)
      LDAC high

    The 3-byte SPI write and read-back works for all the other registers.  Is the data register unique in any way?  I would think that LDAC only controls when the data gets sent to the DAC itself.
    Thanks.

    Joe

  • 0 in reply to jgla
    Prodigy 60 points

    Hello Garrett:
    In the following screenshots,
    DIN7= SCLK
    DIN6= /SYNC
    DIN5= MOSI
    DIN3= MISO
    The host SPI port clock polarity is '0', phase is '1'.  This is the same as what works for the DAC8551 (but not for the DAC8760!)

    Overview of writing 0xc002 to the DAC8775 data register (address 0x5)

    Overview of reading back the data register (address 0x85).  The first instruction is 0x85 00 00.  The second instruction is 0x00 00 00.  Readback value is 0x85 00 00


    Expanded view of reading back the data register (address 0x85), first 14 SCLKs:

    Read back the DAC select register; value is 0x83 00 20 (DAC 'A'):


    Read back the DAC config register; value is 0x84 90 00 (SCLIM= 20mA, HART off, output enabled, slew off, range= 5V):

    Thanks.
    Joe

  • 0 in reply to jgla
    TI__Expert 5820 points

    Hi Joe,

    Thanks for providing the SPI waveforms. I checked them and agree with your assessment. You said that you pull LDAC low before the rising edge of SYNC. In this case the device should operate in asynchronous mode and ignore the following toggling of LDAC. Why do you toggle LDAC if you are using asynchronous mode? I don't think this will cause an issue but can you try keeping the LDAC pin low at all times?

    Also, to make sure nothing is going wrong in configuration try the minimum commands to read and write to the DAC data register.

    1. Reset

    2. Write to select DAC register

    3. Write to DAC data register

    4. Read from DAC data register

    If this works we can debug what is going on with your configuration setup. I recommending trying this and holding LDAC low at the same time.

    Thanks,
    Garrett

  • 0 in reply to jgla
    TI__Expert 5820 points
    Hi Joe,

    Do you have an update on your DAC data register read back issue? Did you using the minimum commands to isolate the issue as I described previously?

    Thanks,
    Garrett
  • 0 in reply to Garrett Satterfield
    Prodigy 60 points
    Thanks, Garrett. Once I confirmed that I could get the DACs working in a minimal async mode, I got them working in synchronous mode. I suspect a reset configuration was keeping the DAC data register at a zero value.
    Joe