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ADC14X250EVM: LMK04828 Device clock/SYSREF generation and its relation with EXTREF

Lizon Maharjan
Intellectual 420 points
Part Number: ADC14X250EVM
Other Parts Discussed in Thread: LMK04828

Hello,

I am currently working with ADC14X250EVM and TSW14J56EVM. I was previously using the clk input on the ADC EVM and using the default LMK04828 configuration from the ADC GUI. I have now changed the circuit of the EVM to provide ADC sampling clock from LMK04828 as suggested in section 5.1.1 of manual Slau625. However, in the process I realize that the system works and the FPGA captures the waveform fine without providing EXTREF. Right now I do not have any clock input to the boards, and it works fine. So, I was wondering what was the purpose of having EXTREF and am I doing something wrong by not providing EXTREF?

Is EXTREF provided for deterministic latency or is there any other reason behind this?

Also, can I use TICS pro through the ADC14X250EVM's USB connection?

Thank you

Lizon

  • 0
    TI__Expert 3515 points
    Hi Lizon,
    EXTREF input to the ADC EVM gives you the option to lock the onboard VCXO to an external reference. if you don't provide EXTREF, the VCXO is free running. The EXTREF will typically be the system clock which gets "cleaned" by the VCXO before being fed into PLL2 of LMK. Please refer to www.ti.com/.../lmk04828.pdf (secton 9.1.1) for more details.
    I don't think you can use TICS pro with the ADC EVM. You can save the register settings and then load them using ADC EVM GUI.
    Regards,
    satish.
  • 0 in reply to Satish Uppathil
    Intellectual 420 points
    Hi Satish,
    So currently, I am skipping the PLL1, and running only PLL2. The documentation you referred tells me that there will be higher phase noise in low offset frequencies, is this the only consequence of not using PLL1 and letting the VCXO run free without the external reference?
  • 0 in reply to Lizon Maharjan
    TI__Expert 3515 points
    Yes regarding PLL1.
    Didn't understand your 2nd point. Can you point me to that paragraph? or copy/paste that part.
    Satish.
  • 0 in reply to Satish Uppathil
    Intellectual 420 points

    Satish,

    So when it says "external VCXO's phase noise dominates the final output phase noise at low offset frequencies", it is referring to EXTREF right?

    Well regardless, I think I should rephrase my question to : If I choose not to use EXTREF and skip PLL1, what are the consequences? or What do give up by deciding to skip PLL1 and to let the internal VCXO run freely?

    PS. Thanks for your timely response, I appreciate it.

    Lizon

  • 0 in reply to Lizon Maharjan
    TI__Expert 3515 points
    external VCXO is not EXTREF. Its the on-board VCXO (Crystek part).
    if you don't feed EXTREF, the reference clock to PLL2 is the free-running VCXO. You're giving up the exactness of your frequency as the VCXO will drift over time and you won't be able to lock it to an external reference.
    Regards,
    satish
  • 0 in reply to Satish Uppathil
    Intellectual 420 points
    That solved my problem. Thank you Satish!!