Hi
i am using ADC08D1500.
i saw that there are two possible DDR clock phase - 0 deg and 90 deg on DCLK clock.
1) Is it possible that the difference between DCLK and Data in o deg is +/-50ps?
2) does it mean that in 90 deg there are valid slack of 960 ps and in 0 deg 1456 ps (in cycle of 1556 ps)?
i saw that there is PITFALLS comments that "Failure to write all register locations when using extended control mode"
3) Does it mean that there is need to write all registers? what should be the results when writes done only to offset registers (2h & Ah)? or no write at all?
Thanks Gilad