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ADC08D1500: timing with I/Q channels

Gilad Aloni
Prodigy 50 points
Part Number: ADC08D1500

Hi

i am using ADC08D1500.

i saw that there are two possible DDR clock phase - 0 deg and 90 deg on DCLK clock.

1) Is it possible that the difference between DCLK and Data in o deg is +/-50ps?

2) does it mean that in 90 deg there are valid slack of 960 ps and in  0 deg 1456 ps (in cycle of 1556 ps)?

i saw that there is PITFALLS comments that "Failure to write all register locations when using extended control mode"

3) Does it mean that there is need to write all registers?  what should be the results when writes done only to offset registers (2h & Ah)? or no write at all?

Thanks Gilad

  • 0
    TI__Mastermind 44290 points

    Hi Gilad

    Regarding your questions. 

    1. Typical skew from DCLK to DATA in 0-degree DDR mode is +/-50ps or less. Variation over process, temperature and power supply range can increase the skew somewhat.
    A DCLK cycle of 1556ps corresponds to an input clock frequency of approximately 1285.34 MHz.
    1. With this DCLK period your calculation of 'slack' is correct for 0 degree mode.
    2. For 90-degree mode the Setup and Hold time values will each increase by 1/2 of the increase in DCLK period from the datasheet condition of 1500 MHz input clock rate to your case of 1285.34 MHz clock rate. So we now have a Set-Up Time of 400 + 223/2 = 511.5ps and a Hold Time of 560 + 223/3 = 671.5ps. These add to 1183 ps.
    3. Since the values in the datasheet are typical only it would be good practice to reduce the slack to provide additional margin. I would recommend taking the typical skew, Set-Up and Hold time numbers and adding +/- 100 ps of additional guard band to provide margin in your system timing calculations. This will reduce your slack numbers by 200ps.
    • If you are using Extended Control Mode where the serial configuration interface is enabled you should do the following:
      1. If you want to write to any registers to change settings it is necessary to write to all registers with the default or desired user values. 
      2. Writing to only one or a few registers can result in unknown values in the registers that have not been written to.
      3. Writing to no registers is OK. But in this case there is no reason to enable Extended Control Mode. It would make more sense to keep the ADC in non-Extended Control Mode.

    I hope this helps answer your questions. Please let us know if you need anything else.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 50 points
    Hi Jim
    i didn't understand the timing calculation that you made in 2.
    can you clarify it?

    in my design
    the input clock to diff pins 18,19 = 1280MHz
    DCLK = 320Mhz
    DDR Mode - so the cycle of each sample is 1562.5ps and not as i wrote (by mistake) 1556ps.
    Thanks Gilad
  • 0 in reply to Gilad Aloni
    TI__Mastermind 44290 points

    Hi Gilad

    For 1280 MHz clock and 1:2 demux the output data rate is 1280MHz/2 = 640MHz. Therefore the data bit time is 1562.5ps as you say. So the data bit time increases from 1333.3333ps to 1562.5ps, which is an increase of 229.17ps. 

    I have recalculated the values as follows (I also corrected my typo where I put /3 instead of /2 in the Hold Time calculation:

    For 90-degree mode the Setup and Hold time values will each increase by 1/2 of the increase in DCLK period from the datasheet condition of 1500MHz input clock rate to your case of 1280MHz clock rate. So we now have a Set-Up Time of 400 + 229.17/2 = 514.59ps and a Hold Time of 560 + 229.17/2 = 674.59ps. The total of Setup and Hold times is 1189.2ps.

    As noted you should reduce this value to provide margin in the system timing calculations. Reducing by 200ps total as recommended gives 989.17ps.

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 50 points

    Hi Jim

    Thanks for your answers

    Gilad