Part Number: DAC3482EVM
DEARS.
I operated EVM in external mode.
How can I use internal PLL to drive DAC3482EVM?
Clock : 245.76Mhz x 4(interpolation),
interpolation : x4
Internal PLL is used.
Thank you.
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Part Number: DAC3482EVM
DEARS.
I operated EVM in external mode.
How can I use internal PLL to drive DAC3482EVM?
Clock : 245.76Mhz x 4(interpolation),
interpolation : x4
Internal PLL is used.
Thank you.
Henry,
You may use the attached configuration file for DAC3484, 4x interpolation, 983.04MSPS sampling as a starting point to understand PLL configuration. You can then make slight adjustments to your DAC3482 configuration for dual DAC (either 16-bit bus or 8-bit bus LVDS interface) configuration.
x00 xF288 x01 x0100 x02 x8052 x03 xA001 x04 xFFFF x05 x0000 x06 x3600 x07 xFFFF x08 x0000 x09 x8000 x0A x0000 x0B x0000 x0C x05A6 x0D x05A6 x0E x05A6 x0F x05A6 x10 x0000 x11 x0000 x12 x0000 x13 x0000 x14 x0000 x15 x07D0 x16 x0000 x17 x07D0 x18 x205F x19 x10F4 x1A x4820 x1B x0800 x1C x0000 x1D x0000 x1E x1188 x1F x8882 x20 x2400 x22 x1B1B x23 x001F x24 x1000 x25 x7A7A x26 xB6B6 x27 xEAEA x28 x4545 x29 x1A1A x2A x1616 x2B xAAAA x2C xC6C6 x2D x0000 x2E x0000 x2F x0000 x30 x61A8 x7F x0001 CDCE62005 Registers Freq:19.200000MHz Address Data 00 80400000 01 811C0321 02 81400302 03 81040303 04 00040304 05 38101A85 06 04BF1F66 07 151877F7 08 20001808
-Kang
Hello Henry,
For the PLL mode that I send you, there is no need to apply clock to J9 as the CDCE62005 is self generating the 983.04MHz clock to the DAC3482. The CDCE62005 itself is a clock multiplier using the 19.2MHz crystal to create the 983.04MHz clock.
you may then use the 983.04MHz clock as reference to the DAC3482 PLL. The PLL can take the 983.04MHz, and then divide and multiply to generate the on-chip 983.04MHz clock. (note: this is not how people typically use the DAC3482 PLL. This is purely for testing purpose. You may later change the clock from the CDCE62005 to lower reference like 245.76MHz or 491.52MHz, and then change the DAC3482 M/N divider ratio to generate the 983.04MHz clock.)
The PLL reset should not be used. This fixed the PFD loop filter voltage at half the VCO bias, and disable any locking capability. You should uncheck this button.
Also, the OSTR signal in PLL mode is the PLL PFD frequency. You will need to consider the PLL PFD as the new OSTR signal. For testing purpose, I recommend you disable the use of the OSTR signal. The two diagrams below show my setup:
I have circled the change from OSTR to frame signal to relax the OSTR (PFD) requirement.