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DAC38RF89: DAC38RF89 LMFSHD = 42111 (dual independent DACs with complex input data) I & Q synchronization

Douglas Farinelli
Prodigy 90 points
Part Number: DAC38RF89

Currently experiencing what appears to be a delay offset between I and Q data (potentially a delay difference on a lane basis i.e. individual bytes).  I can't tell from the datasheet what the data path looks like. The datasheet refers to a JESD_FIFO and a JESD_RBD_Buffer (don't know if these are one in the same or independent).  My assumption is that the JESD write is not an issue (protocol will align data).  However like to understand what mechanism are available to synchronize the reads. 

  • 0
    TI__Genius 9695 points
    Hi Douglas,

    Can you confirm you are following the startup procedure in datasheet figure 141 because this will ensure all the datapaths are correctly synchronized.
    If you are using the mixer+NCOs can you also make sure you are synchronizing these after writing the NCO frequency word?

    Thanks,
    Eben.
  • 0 in reply to Ebenezer Dwobeng
    Prodigy 90 points

    I have reviewed the software and it is implementing figure 141.  We are using mixer + NCOs and have synchronized after writing to the NCO frequency word (even changed the sync methods).  I need to verify signal integrity (we have hyperlynx sims but I haven't put a scope on the signals).   One question on figure 141 ... when it states ensure at least two sysrefs ... I'm using a single pulse sysref generator and requesting the pulses using a blocking function that should not return until the pulse has been issued.  While the sysref will be on a proper clock cycle (cyclic) it might not be on the next cycle as in a free running sysref generator and I'm only generating two sysref pulses as defined by figure 141.

  • 0 in reply to Douglas Farinelli
    TI__Genius 9695 points
    Hi Douglas,

    Since you are using only 2 SYSREF pulses that are sparsely spaced, DC coupling to the SYSREF interface of DAC is recommended. Can you confirm you are DC coupling to SYSREF and also check the common mode voltage is 500mV? AC coupling to SYSREF is suitable for free running SYSREF clocks. Also, if you can generate continuous SYSREF to the DAC and FPGA, can you check if this helps to resolve the issue? I believe the issue is likely the I and Q datapaths are not synched and so have different latency.


    Thanks,
    Eben.
  • 0 in reply to Ebenezer Dwobeng
    Prodigy 90 points

    We are DC coupled.  I modified the board to set the common mode to 0.5V.  This did not solve the problem.