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ADS8900B: SPI interface compatibility with Xilinx AXI Quad SPI IP

Praveen Mulimani
Prodigy 10 points
Part Number: ADS8900B

Hi All,

I am developing a design where i use ADS8900B to monitor the current supplied to one of the module on the board.  I want to use "Xilinx AXI quad SPI IP" in master mode  to communicate with SPI slave on ADS8900B module. I just checked the SPI interface of  Xilinx SPI and compared with ADS8900B, i am unable to decide how to connect the MOSI -MISO lines, as Xilinx gives 4 MOSI and 4 MISO lines and ADS8900B has only 1 MOSI and 4 MISO lines.

Please help me out with this. For reference i have attached the datasheet of Xilinx Quad SPI below.

pg153-axi-quad-spi.pdf

  • 0
    TI__Mastermind 43000 points
    Hi Praveen,

    I suggest reaching out to Xilinx on the details of configuring the IP module.

    For quad SPI, the ADS8900B requires at least 5 SCLK's to clock out the reading result or register contents (Table 7 in the datasheet). If you also want to read the parity bits, then 6 SCLK's are needed. If you want to keep the data transfer to a standard 8 bits, you can use 8 SCLK's. When reading the conversion result, you can hold the ADS8900B SDI input either high or low.

    In order to write to the internal registers, you must clock at least 22 bits into SDI. You can clock more than 22 bits, i.e., 24bits, by adding two zeros and then the 22b command, per Tables 2 and 4 in the datasheet.

    As long as the Xilinx core is flexible enough to read 5-8b in quad, MISO mode and write 22-24b in single, MOSI mode, you should be able to get it to work.

    Regards,
    Keith N.
    Precision ADC Applications