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ADS7039-Q1: SPI timing, 16 SCK pulses input

RYUJI SAITO
Prodigy 20 points
Part Number: ADS7039-Q1

Hello

I will have to input 16 SCK clocks to ADS7039, during the period of /CS=L,

as shown in the diagram, because of the restriction of the SPI function of my processor.

Now I wonder how does ADS7039 react to these extra SCK pulses.

Can ADS7039 output correct data with the leading 12 pulses anyway, so that we can just ignore the last 4 bit data?

Thank you very much in advance.

Ryuji Saito

  • 0
    TI__Guru* 93045 points
    Ryuji-san,


    Our recommendation is that you follow the guideline that you use 12 SCLKs to clock out the data and then return the /CS high. I don't know of any specific mode the device enters when you clock out 16 SCLKs. However, on the first clocking of after power-up, if there are 16 SCLKs the device enters offset calibration.

    Again, we just recommend sending the 12 SCLKs for reading the data.


    Joseph Wu
  • 0 in reply to Joseph Wu
    Prodigy 20 points

    Thank you vey much Joseph

    I will study how to do with this with my SoC.

    Ryuji Saito