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ADS5294EVM: receiving the frame clock and bit clock through FPGA.

Part Number: ADS5294EVM
Other Parts Discussed in Thread: ADS5294

hi 

we are using ADS5294 EVM to be interfaced with KC705(kintex-7 EVM)

we need to deserilize the LVDS data in FPGA

for this we used the sync test pattern and checked for the bit_clock and Frame_clock in ILA

but the bit_clock and Frame_clk are not coming as suggested in ADS5294 datasheet.

and other control need to be set to get the bit_clk and frame_clock ?

Thanks 

prateek

  • Hi Prateek,
    How are you?
    Thanks for using ADS5294 device.
    For your question about the LVDS output signals, I will reply to you in two days.
    Thank you!
    Best regards,
    Chen
  • Hi Prateek,
    When the ADS5294 data output will send out Frame Clock signal by setting LVDS mode
    to take an action (to align with FPGA, for example).
    Therefore, please try the following register settings first
    to make sure the device is set up correctly.
    First, please make sure ADS5294 input Clock CLKIN must be turned on.
    then, Here is the example:
    (soft reset, 1-wire mode, 14bit mode)
    (in this case, we set SYNC PATTERN mode)
    Address=0x00, Data=0x0000
    Address=0x42, Data=0x8000
    Address=0x46, Data=0x8400
    Address=0x25, Data=0x0000
    Address=0x45, Data=0x0002

    (you also can try: the following is set RAMP PATTERN mode)
    Address=0x45, Data=0x0000
    Address=0x25, Data=0x0040

    Thank you!

    Best regards,
    Chen