TSW14J56EVM: DAC Format Pattern, ADC Bit Packing Channel Pattern (multiple devices)

Justin,

I am assuming you have a custom board with 2 ADC's and 2 DAC's and one FMC connector that you are connecting to a TSW14J56EVM, correct? What is the clocking source? Can you send a schematic of this? Are you then trying to operate the TSW14J56 in a transceiver mode? if so, what is the LMF settings for each link?

When operating the TSW14J56EVM in a transceiver mode, the software will require a separate ini for the ADC and one for the DAC. Both ini files will need the following line added to it for this to work:

Transceiver Mode = 1

Normally we would load the DAC ini first followed by the ADC. The GUI then would be used to capture data from the ADC. Attached are two example ini files used in this mode.  

Regards,

Jim

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/73/AFE74xx_5F00_RX_5F00_Mode6_5F00_XCVR.inihttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/73/AFE_5F00_ADC_5F00_442_5F00_FBRX_5F00_TRX.ini

Hi Jim,

That's correct.  I have a dual-DAC board connected to the eval board through the FMC, with a dual ADC daughter board stacked on the DAC board.  clock and data signals are passed through a differential connector between the two boards.  Clocking is achieved through a single LMK04828 located on the DAC board.  A second jesd clock and sysref have been routed to unused pins on the FPGA eval board for use in the second jesd communication bus. Schematic files are attached.

LMF for the DAC is 442, ADC is 484.  Because of that, I'm going to break the FPGA into a TX and RX section of JESD.  It will be used as a transceiver, but everything will be hard coded into the FPGA, rather than being read in on power up.  I'm using the INI files to make sure I have the right variables for each leg, rather than trying to debug the hard-coded values.  As long as I can get the 8 TX and 8 RX channels working in unison, I feel confident we'll be able to get the transceiver functional.

I'm currently looking through the FPGA code to make sure I get all of the required changes implemented, so I want to make sure I understand all of the variables in the INI files and how they get imported.

Thanks for your time.

Justin

10124-ADC.pdf10127-DAC.pdf

Justin,

See attached files for more info regarding the ini files.

Regards,

Jim

TSW14J56revD ADC INI File Guide (2).docx0777.TSW14J56 DAC INI File.docx

Thanks, Jim, that helps a ton.  I've been working with the DAC outputs thus far, so I'll start there to make sure I understand and to see what might be happening in my outputs.

In the format pattern, the first number is the MSB (+X) or LSB (-X) for the channel in question (X).  The second number is the sample... so -1 should be the I and -2 should be the Q.  The "X-3, -X-3, X-4, -X-4" that i mentioned in my initial post, which is included in the default INI file, really isn't needed, correct?  That would just be sample 3 (I) and sample 4 (Q).  That COULD be repeated with -5,-6; -7,-8; etc, but it's not necessary.  Thus, "X-1, -X-1, X-2, -X-2" for X=1:8 is sufficient to declare all 8 channels. 

And, as you had mentioned in a previous post of mine, the waveform file should include 8 I and Q files, in order, for a total of 16 columns (csv).  1I,1Q, 2I,2Q, etc.

Assuming I have that correct, the outputs I'm seeing on the DAC are quite strange.  I'm not sure if I have something incorrect in my INI file or possibly a setting in the DAC. 

For troubleshooting purposes, I created multiple files that use a different waveform for every channel.  When I load one of these that contains all 16 columns, the output waveform looks like noise on the spectrum analyzer.  If all 8 channels contain the same data, the outputs look fine, except every other channel is shifted by 90*.  Ie: ch1:0*, ch2:90*; ch3:0*; ch4:90*, etc.

With that in mind, I went back to my multi-waveform files and reduced the file to only 8 columns.  When I do this, things work fine, although the phase shift above still holds.  I suspected that the waveforms were getting pulled in as real rather than complex, which would result in the second reading being shifted 90* from the first.  After a bit of waveform manipulation, I ended up trying something where my I and Q files contain different frequencies with only the first channel. Additional channels remained sine waves.

With an "i" term at 1MHz and a "Q" term at 10MHz, the channel 1 output was a "warbled" sine, with a 10MHz signal riding on top of a 1MHz signal.  That confirms that the I and Q terms are getting combined.  However, when I looked at ch2, the exact same signal was there, only shifted 90*.  The same warbled sine, just shifted.  Ch3 output was a sine, ch4 output was a sine that was again shifted 90*.

Based on this, it seems that the I and Q values are getting combined correctly, but for some reason the signal is getting shifted 90* and output to the next channel, as well.  I don't know if this could be caused by a DAC register setting, INI file setting, or an incorrect format pattern declaration.

I've attached my INI file and waveform file, if needed - site didn't like the csv extension, so I changed it to txt.  The waveform file started out as an alternating 1MHz/10MHz signal (every other channel was a different freq), and I simply copied column 3 and pasted it in column 2.  That gave me the different freqs of I and Q (theoretically).

Thanks for your help, Jim

Justin

Comp_half_I_alt.txt

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/73/1067.DAC3XJ84_5F00_LMF_5F00_442_5F00_8CH.ini

I connected the DAC EVM up today, using the standard INI file and some of the test waveforms I was using before and the behavior is the same on that setup.  It seems like ch1 and ch2 share a set of data and 3/4 share a set of data.  Again, I'm hoping this has something to do with the Format Pattern of the INI file, but everything I've tried so far has failed.  Hopefully what we're looking to do is possible with this device.

All output channels fed by a unique waveform, however the internal mixer is the same across all channels.  I'm hoping to go +/-125MHz about Fs/4, but each channel will vary slightly in amplitude and phase.  All of the examples I've looked at look to share data between 1/2 and 3/4, as I said.

I was imagining a 16 column waveform where each pair of columns is an I,Q set for one channel.

Is this possible?

Thanks,

Justin

Justin,

Is this still an issue? If so,

1. Can you share the INIs that the customer had shared (as mentioned in the word file)?

2. Is it possible to get a diagram/details on how serdes lanes are routed from the 2 ADCs/2 DACs to the J56?

It looks like there might be some INI formatting issue when combining the mode for two device capture. Also we expect the clocks to the ADC/DACs are from a common referenced signal source. Please confirm if this is true.

Regards,

Jim

Hi Jim,

It's still an issue.  I've tried numerous file patterns and I can't seem to find one that work properly.

1.  My ini file (and a waveform file) are about 2 posts back.  A few of the file patterns I've tried are in there and commented out.  I tried a few more since then, but it was really shots in the dark, including treating each column as a "sample" (ie 2-3 would be the MSB of ch2 from column 3).

2. I uploaded a pdf of both the ADC and DAC schems above.  The ADCs seem to be working properly, as far as I can tell.  I'll try to do some phase shifting on adjacent channels to make sure, but the frequencies come through fine.

In general, though, my serdes lines match up to the FPGA 1-1.  TX0 -> DAC1 Lane 0; TX3 -> DAC1 Lane 3; TX4 -> DAC2 Lane 0; TX7 ->DAC2 Lane 3.  The same holds true for the RX lanes on the ADCs.

I'll be modifying the FPGA code to account for the different settings between RX and TX, hard coding the values for each path... and they will have separate clocks, as well (common sysref freq).  My clocks are all coming from a single LMK04828, but each path has a dedicated channel as they don't operate at the same DCLK freq.

I have yet to attempt to operate the system in transceiver mode, though.  I want to make sure I fully understand each path and the configs required while I update the code as needed.  All the testing pertaining to this issue has been done in a TX-only configuration. 

Also, as mentioned, I see the same behavior on my board and the DAC EVM.  Ch2 is always a 90* shift of ch1; same of ch 4 and 3, 6 and 5, 8 and 7.  I have yet to be able to put out a different frequency or an intentional phase shift on ch 1 and ch 2.

Thanks for your help,

Justin