THS1206: Data_AV issue

Hi Johnson,

Without seeing any timing from the system, the only suggestion that I have at the moment is to go back and review the datasheet again.  The THS1206 is a pipeline converter and there are specific instructions in the datasheet on when to start applying the RD impulse based on the configuration of the device and the FIFO trigger level.  Please provide screen captures of the control lines and we can help you debug this further.

Hi Team,

1: The initial configuration timing of the system is as follows (1st diagram):
1.1 After power-on, first write RESET reset information to HS1206. H'401
1.2 Clear reset H'400
1.3 Write working mode to CR0 H'098
1.4 Write FIFO reset control signal / CR1 mode configuration H'492
1.5 Clear FIFO Reset H'490

Thank you Johnson,

Can you get a logic analyzer capture that shows the test bench capture? Please include the initialization sequence up to the first batch of read cycles.

Hi Tom,

Below is the abnormal (top) vs normal (bottom) initialization sequence up comparison. 

Since the FPGA is uninterrupted power down, and the reconfiguration time is likely to be reconfigured at CS0 = 0 / CS1 = 1, due to the status of CS0 / CS1 may be inconsistent during this initialization.
However, there is a global reset instruction in the initialization operation, which should not be subjected to the CS0 / CS1 state before the configuration reset influences.

Could you help to look into this issue?