Hello,
I plan to interface a SPI interface into the DDC232 and I wanted to know if it was okay to route the same clk bus to CLK_CFG and DCLK. The datasheet state that CLK and DCLK should be different (though from the same source), but does not stipulate anything for CLK_CFG. How I understand it is that after switching to regular mode from the initial configuration, the CFG pins are not in use.
Is it okay if CLK_CFG gets clock pulses during normal operation?
Planned interface setup:
SPI CLK - > CLK_CFG & DCLK
SPI MOSI -> DIN_CFG
SPI MISO -> DOUT
MCU PLL divided Clock out -> CLK
Thanks for the clarification!
