TLV2556: Need specs verification

Hi Hariharan,

Welcome to our e2e forum!  What sort of information are you looking for with regards to the TLV2556?

Hi Tom, Thanks for helping me. I have two outstanding questions on the data sheetTLV2556.

1. On page 22, CFGR2, D1 is configure EOC/INT pin and D0 is for default configuration. Can they use both in a configuration because the default configuration should either EOC or INT. what is exactly configured in default configuration? EOC or INT

2. On page 25, all 4 bit addresses are taken and the document says 1111 is used to configure CFGR2 and any other address bit for the CFGR1 registers. what is this any other address bit when all other options are taken for some other functions?

Could you reply to me as soon as possible?

Thanks
Hari

Hi Hari,

The four MSB's of the SDI are considered the address bits. You actually need to write to CFGR2 first (see Figs 1 and 2 and review the text on page 10). So writing 0xFx gets you to CFGR2, and you can setup the reference, pick EOC or INT. The 'default' mode of CFGR1 is somewhat confusing since you have to write the full 8-bits for each command cycle. The four MSB's in this case would be 0x0 through 0xA to address each channel and the four LSB's would normally remain constant.

Tom,

Thanks for your reply. Could you explain me more on your reply.

 

 

 The four MSB's of the SDI are considered the address bits. You actually need to write to CFGR2 first (see Figs 1 and 2 and review the text on page 10). So writing 0xFx gets you to CFGR2,  I understood here and no confusing

 

and you can setup the reference, pick EOC or INT. When I set up for EOC how do I configure default mode. What is this default mode means? My concern was this default mode set EOC or INT by default. The default mode is common for both CFGR2 and CFGR1.

The 'default' mode of CFGR1 is somewhat confusing since you have to write the full 8-bits for each command cycle. The four MSB's in this case would be 0x0 through 0xA to address each channel and the four LSB's would normally remain constant. The MSB 0x0 through 0xA  addresses are taken for some other functions. It is described in the same page number. What is differentiate the address that is only used for CFGR1.  When I set LSB 4 bits a constant value  to what is configured. What is this constant value? Can I set any constant value?

Thanks

Hari

Tom,
Thanks for your reply. I have another two question.
1. most timing diagram shows both EOC and INT has to be configured . it is the same pin so I believe only one can configure at a time. please clarify?
2. the EOC goes low after the8th clock pulse and next CFGR1 is configured at 12th clock pulse. is this is true should I assume like tconv should be within three clock delays.
3. should I assume EOC is as acknowledgement for the CFGR2 writing complete acknowledgment? and I believe EOC goes low again for CFGR1 write complete acknowledgement.
4. data sheet says we have 11 select analog channels, so should I assume each channel uses a set of CFGR1 and CFGR2 registers?

thanks for help
Hari

Hi Hari,

Pin 19 on the TLV2556 can be configured as either 'End Of Conversion' (EOC) or as an 'Interrupt' (INT). Using Figures 3 and 4 as reference, the TLV2556 uses the first four SDI (DATA IN) bits to switch the MUX to the desired sample channel. This is the Access Cycle using the address bits we talked about earlier. During the Sample Cycle, the sample and hold switch is closed against the desired input channel. Once the sampling is complete, the conversion process starts.

In EOC mode, pin 19 will output a low logic signal while the conversion process is taking place. Once the conversion is complete, the output on pin 19 will automatically go high. It will stay high and only transitions back to a low state again once the next conversion cycle is started. If pin 19 is configured as INT, the output behaves a little differently. The output transitions from high to low once the conversion is complete. Basically the rising edge of EOC mode is the same thing as the falling edge in INT mode.

The EOC signal goes after the eighth or twelfth clock depending on how you have CFGR1 setup. The EOC signal is only for the conversion process, it is not an acknowledgement of any configuration register write.

CFGR1 and CFGR2 are not channel specific - these both pertain to the entire chip. If you take a look at the Functional Block Diagram in section 8.2, everything to the right of the 14-channel Multiplexer is controller by the configuration registers. I suppose you could change modes between channels, but that would be a rather unusual way to use the TLV2556. Normally you configure CFGR2 , and then leave the low nibble fixed as I mentioned before.

Tom,
thanks for your reply . can we chat for 10 mins? 4073560892
thanks