ADC128S102QML-SP: Gain and offset error match

Hello Mark,

Since your question is really about the THS1206, I am moving this thread to the group that covers that part.

Kirby

Hello,

I will let our local expert elaborate on this but I predict it is because when the THS1206 was release, which was in 1999, this information was not gathered. This could be due to limitation in technology at the time, or various other reason.

The ADC128S102 was released in 2008, about a decade after the THS1206 was, and this information was now included in the datasheet.

In short, I would suggest not assume that the THS1206 does not have such errors.

Regards,

Cynthia

Hello Tom,

  Thank you for your response.  No apologies necessary and thank you for the welcome.  My questions stems from ratiometric demodulation of LVDT signals.  If the ADC channels are matched well, then the ratio of the LVDT secondaries will divide any matching errors out.  However, if the matching is not that well, then that assumption does not stand.  My question is then:  is the matching dependent on the type (i.e. SAR, Flash, Sigma - Delta) and process technology of the ADC, even though the ADC input channels are on the same monolithic IC?  Is the gain and offset error the same for every input channel, while the gain and offset error match different channel to channel?  What is a typical gain and offset error match parameter if it is not listed?  Is it about 1.5 LSB?  Is the max and min channel matching 4 sigma as your training videos state?  Thank you very much.

Mark Khusid

Electrical Design Engineer

Moog, Inc.

Tom Hendrick said:

Hi Mark,

I'm sorry to see you get passed around this way, so do let me apologize and welcome you to our e2e forum!  If your query really is about the THS1206, as Cynthia noted, this is an older part and gain error matching by channel data is not available for this device.  If your question is about the ADC128S102QML device, the offset and full scale errors are significantly better than the THS1206 (by nearly an order of magnitude).  You are correct in your understanding of the 'match' parameters in the datasheet(s).

Hi Mark,

OK - I see your point.  My concern here is that the ADC128S102 has a single ended MUXed input with one sample/hold circuit, where the THS1206 has four sample/hold circuits followed by a single ended or differential mode MUX.  From my experience, the ADC type is not the driving factor in channel to channel matching.  An ADC with multiple simultaneous sampling inputs can have similar matching channel to channel regardless of it being a SAR or sigma-delta converter - that comes down to input routing and aperture delays on the S/H switches for the most part.  Older SI technologies can have larger, slower gates, which can impact matching.

In general, you won't see much difference across all channels of one device, but you may see some differences between devices due to lot-to-lot variation and process corners.  I'm not sure which training video you are referring to with the 4-sigma matching, can you point me to the URL and I'll give you further comments on that.