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CCS/ADS1274: FSYNC input in Frame-Sync

Joonbum Kim45
Intellectual 310 points
Part Number: ADS1274

Tool/software: Code Composer Studio

Data rate is 10,547SPS in Low-Speed mode.

Does it mean that the ADS1274 chip produces 10,547 measurements per second?

Does DRDY interrupt occur 10,547 times per second in SPI mode?

Should the MCU control the FSYNC pin 10,547 times per second in Frame Sync mode?

If I read 10k times, is there a problem with the data quality?

I'm worried that 10,547 times per second will be controlled correctly by a MCU timer.

If I need 22kSPS, how do I set it up and how do I read it?

  • 0
    TI__Mastermind 37690 points

    Hello Joonbum,

    Yes, in low speed mode with master CLK=27MHz, CLKDIV=1, each of the 4 ADC's will output data at a rate of 10.547ksps. In SPI mode, DRDY will toggle at a rate of 10.547ksps.

    If using Frame-Sync mode, then yes, the MCU must provide a Frame-Sync pulse at the desired output data rate, or 10.547ksps in this example.

    The ADS1274 continuously converts data at the output data rate. In SPI mode, the MCU must monitor the DRDY, and when it toggles, read the data out of the device before the next DRDY, or you could get data corruption. In frame-sync mode, FSYNC must be set to an integer multiple of CLK periods. For this example, the period of FSYNC must be 2560*t-CLK to achieve 10.547ksps output data rate.

    In both of the above cases, if you want to run at 10ksps, you should adjust the CLK frequency. For the low speed example, the output data rate is equal to Fclk/2560 (CLKDIV=1). In order to set the output data rate to 10ksps, Fclk=10k*2560=25.6MHz.

    If you would like to convert data at 22ksps, I suggest using SPI as this is easier to implement on an MCU. You can use any mode other than Low-Speed mode and adjust the CLK frequency accordingly.

    For example:

    CLKDIV=1

    High-Resolution MODE

    Output Data Rate = fCLK/512

    fCLK=22ksps*512=11.264MHz.

    Regards,

    Keith Nicholas
    Precision ADC Applications