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DAC81408: Need further explanation or DAC update rate.

Louis Morrison
Prodigy 110 points
Part Number: DAC81408

The datasheet states:

A DAC trigger signal is generated either through the LDAC bit or by the LDAC pin. The synchronous update mode enables simultaneous update of multiple DAC outputs. In both update modes a minimum wait time of 1 µs is required between DAC output updates.

Does this infer that the CS pin cannot low for 1uS after LDAC is asserted?

In addition, what is the tDACWAIT specified in the datasheet in reference to? Is this and the above specs on the analog side or the digital side of the chip?

Lou

  • 0
    TI__Genius 14220 points

    Hi Louis,

    Thank you for your query. I am checking with the design team regarding the timing specs. I will get back to you tomorrow.

    Regards,

    Uttam Sahu

    Applications Engineer, Precision DAC

  • 0 in reply to Uttam Sahu
    TI__Genius 14220 points

    Hi Louis,

    Sorry for the delay. I checked with the design team. Please consider the value provided in the spec table in section 7.6. The "1us" value mentioned in the text is a typo. Please ignore it.

    Hope that answers your question.

    Regards,

    Uttam

  • 0 in reply to Uttam Sahu
    Prodigy 110 points

    Hello Uttam,

    I guess I still don't understand the specification in the datasheet. Is the tDACWAIT specified the amount of time it takes for the internal logic to migrate the data from Register B to register A or is it the time it takes for the DAC to output the changed data? What is the "wait" referring to? tDACWAIT is not shown in any timing diagrams so what two signal transitions are defined by the tDACWAIT timing parameter?

    Thanks,

    Lou

  • 0 in reply to Louis Morrison
    TI__Genius 14220 points

    Hi Louis,

    Apologies for the delayed response. The tDACWAIT is the time interval between subsequent LDAC falling edges in synchronous mode or the interval between subsequent CS rising edges in asynchronous mode.

    Sorry for missing this in the timing diagram. we will try to capture that in the next revision.

    Regards,

    Uttam

  • 0 in reply to Uttam Sahu
    Prodigy 110 points

    Hey Uttam,

    Thanks for the clarification.

    I have another spec related question. The SPI clock is 50MHZ and the datasheet says it needs to be High 10nS and low 10nS, which allows for no rise and fall time. Are these parameters key? if I have a 9ns high and 9ns low, would this explain why my design is not working?

    Lou

  • 0 in reply to Louis Morrison
    TI__Genius 14220 points

    Hi Lou,

    Sorry for the late response. The SCLK low and high periods are measured between mid-points of the clock period as shown in the timing diagrams in the datasheet. If your timing is on the border, it might be a good idea to check by reducing the SCLK frequency. this way we can find out whether the timing is the problem or not.

    Regards,

    uttam

  • 0 in reply to Uttam Sahu
    TI__Guru 53633 points

    Hi Louis,

    I am going to close this thread and focus on your other post:https://e2e.ti.com/support/data-converters/f/73/t/855350 as I feel these are really the same problem.  I will also reach out to you over email shortly.

    Thanks,

    Paul