DAC81408: DAC81408 tdacwait

HI Nishie,

I don't have any timing chart for tdacwait.

Basically this is the time you need to give before you attempt to update the same channel with another data. ( Its the digital delay)

Ch1 -- > Tdacwait ----> Ch1

Regards,

AK

Hi AK,

Thank you for your reply.

Is Tdacwait only needed when updating the same channel?

I thought I needed Tdacwait for update different channels（CH1 --> Tdacwait --> CH3） with another data as well.

Best Regards,

Nishie

Hi AK,

Thank you for your reply.

I have an additional question.

Our customer has a CS high 80ns between a register updates to other register update.

And it seems that the data is reflected normally.

With reference to E2E thread "DAC81408: Timing for external LDACn inactive to CSn active.", I think the wait time needs 2.4us, but is 80ns okay?

And could you tell me why the data is reflected with wait time = 80ns?

Our customers update the registers according to the following procedure during DAC operating (Synchronous mode) after initialize setting.

1. Write 16bit data to register address 0x14(or 0x15)

2.CS High 80ns (Red letters in below figure)

3.Write 16bit data to register address 0x16(or 0x17)

4.CS High 80ns

5.Write 16bit data to register address 0x18(or 0x19)

6.CS High 80ns

7.Write 16bit data to register address 0x1A(or 0x1B)

8.LDAC Low 20ns

Best Regards,

Nishie

Hi Nishie,

The tdacwait is the time interval between subsequent LDAC falling edges in synchronous mode or the interval between subsequent CS rising edges in asynchronous mode. Basically, the way tdacwait must be interpreted is as the delay between the latch edge and the CS falling edge of the next DAC command

In the diagram below, second waveform is LDAC.

hope this is clear, we will try to capture this in the datasheet in the next revision.

Regards,

AK

Hi AK,

Thank you for your reply.

I understood Tdacwait.

I have additional question.

you said "Treat these registers as data registers. So the same rules apply" in other thread "e2e.ti.com/.../964108"..

Is there any problem with initial register setting timing?

<initial register setting timing>

1.CS Low

2.write 0x0A04 to address 0x03

3.CS High 80ns

4.CS Low

5.write 0xAAAA to address 0x0B

6.CS High 80ns

same timing as above

7.address 0x0C (data 0xAAAA)-->0x06 (0x0FF0)-->0x14 (0x8000)-->0x15 (0x8000)-->0x16 (0x8000)-->0x17 (0x8000)-->0x18 (0x8000)-->0x19 (0x8000)-->0x1A (0x8000)-->0x1B (0x8000)-->0x0E (0x0010)-->0x09-->(0xF00F)

8.CS High

9.LDAC Low

Best Regards,

Nishie

Hi,

tdacwait is only applicable for data register, not for settings registers like STATUS, SPICONFIG etc.

and tdacwait has to be maintained or both synchronous and asynchronous updates.

To get maximum throughput, send all data for the channels one after the other and use LDAC to update the DAC.

after LDAC goes low, you need to give tdacwait time for next data update.

Hope this is clear now.

Regards,

AK

Hi AK,

I understood setting registers does not need tdacwait.

Are the setting registers from 02h to 0Fh and 21h, 22h?

Is there any problem with the register setting order or CS High time for 1 to 8 of the previous reply (initial register setting timing)?

Best Regards,

Nishie

Hi AK,

We have obtained additional information from our customers.

After that, when the wait time between the registers was set to 3us (> tdacwait), a voltage of 0V was also output from all channels.

Is there any problem with the register setting order or CS High time(wait time) for 1 to 8 of the previous reply (initial register setting timing)?

Best Regards,

Nishie

Hi AK,

Thank you for your reply.

I will set CS High time to more 50ns for setting register (from 0x02h to 0x0Eh).

In additional I will set wait time to more 2.4us for other registers.

Best Regards,

Nishie