I am Using a pair (4 channels) of DAC5689 converters. In the initial design I want to run them in a straight through mode with only an input clock (200MHz) and an output clock running at the same rate. .
My problem is that I cannot get the parts to run. I am getting no output from any of the 4 channels.
here are the register values:
/cfs-file/__key/communityserver-discussions-components-files/73/register-values.xlsx
I am obviously missing something!
Hi Dean,
I have checked your register setting briefly, and please confirm if you are using dual clock mode with you providing differential clock input of 200MHz to latch the 200MSPS of CMOS bus properly. Please probe the differential clock with respect to the CMOS data to double check setup/hold time of the data latch. You are using interpolation by 1x, so make sure that the CLK2 is being driven by differential clock at 200MHz as well. The registers that I have checked are:
Please make sure the DAC output is biased at 3.3V as the DAC is a current sink based architecture and need 3.3V bias as for current mirrors internally. If your output is DC coupled, you may use the serial-data at the input of the DAC to change the serial data around and check the output swing. Make sure the enable serial_data_ena bit and change the serial_data register (based on your setting of offset binary format (register 1, bit 3, two's)) accordingly. For instance, 0xffff is most positive swing, 0x0000 is the most negative swing.
All other settings checked out. This is the most basic setup so I do not see other problems.
