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ADC10D1500CIUT design review

Divya Jyothi1
Intellectual 270 points


Hi, 

can anyone review the attached ADC10D1500CIUT  design and provide the comments if anything is wrong.

thanks & regards,

DivyaADC10D1500 DESIGN.pdf

  • 0
    TI__Mastermind 41980 points

    Hi Divya,

    Yes, I will take a look and provide feedback.

    I will get back to you soon.

    Thank you,

    Rob

  • 0 in reply to Rob Reeder
    TI__Mastermind 41980 points

    Hi Divya,

    The only suggestion I can find is that several of the logic lines in our evaluation board have a series 50ohm resistor.

    For example pins:ADC10D1X00RB.pdf

    U3 PDI

    V3 PDQ

    Y3 FSR

    W4 DDRPHASE

    B3 ECE

    V4 CALDLY

    V5 DES

    This is to slow down any edges and help with termination of these lines from the driver side. It might be good to address this as this is standard practice in connecting digital logic.

    Also attached is the schematic of our EVM design for reference.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Intellectual 270 points

    Hi Rob,

    Thanks for the review comments.

    May i know what kind of impact it can make, if 50 ohm series termination resistors are not added on those control lines ?

    We have used same circuitry in other design, where we are not added 50 ohm series termination on those control lines And that design is working.

    Thanks & regards,

    Divya

  • 0 in reply to Divya Jyothi1
    TI__Mastermind 41980 points

    Hi Divya,

    If this layout is new, it would be worth simulating your low level control lines in Hyperlynx or similar program to understand the overshoot and ringing on each individual control line.

    Typically series resistors are added to help manage this. What can happen is intermittent spi writes to the converter or other ICs for example. in other cases not all registers will be set properly.

    If you are confident it will work then there is no need to add this option. But if the layout has changed...especially if control lines are now longer from the previous revision or design, then it might be worth looking into.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Intellectual 270 points

    Hi Rob,

    One more clarification we need it regarding ADC sample clock input BALUN placement.

    Currently we are generating the Sampling clock to ADC from LMX clock synthesizer and used balun B0430J50100AHF to convert 50ohm  single ended to 100 ohm differential ended signle.

    But BALUN is placed 3384.812 mils from ADC clock input. Is it OK ? 

    Please provide your suggestion.

    Thanks & regards,

    Divya

  • 0 in reply to Divya Jyothi1
    TI__Mastermind 20541 points

    Hi Divya,

    The clock length should be fine. I would recommend using the highest output swing click setting and use a 100 ohm termination placed near the clock inputs of the adc. With AC coupling capacitors after.

     

    Can please verify following question.

    Why aren’t you interfacing the differential outputs of LMX directly with ac coupling caps to differential clock inputs of the  ADC? Why do they need to go through Balun? can you please share the schematic with LMX pages?

     

    Regards,

    Neeraj


  • 0 in reply to Neeraj Gill
    Intellectual 270 points

    Hi Neeraj,

    Since we used B0430J50100AHF 1:2impedance ratio BALUN and it does not requires additional 100 ohm termination.  This is suggested in snaa206 (Schematic and Layout Recommendations for the GSPS ADC).

    We are using LMX2541SQ2690E/NOPB part for generating the ADC clock and the output clock (RFout) is 50 ohm impedance.

    Please find the attached LMX design.LMX2541SQ2690E.pdf

    Thanks & regards,

    Divya

  • 0 in reply to Divya Jyothi1
    TI__Mastermind 20541 points

    Hi Divya,

    Make more sense now.

    Regards,

    Neeraj

  • 0 in reply to Neeraj Gill
    Intellectual 270 points

    Hi Neeraj,

    Please provide clarification of the clock BALUN placement.

    Currently in our board BALUN is placed  3384.812 mils away from the ADC. But in ADC part datasheet they mentioned to place the Clock BALUN very near to the ADC input.

    Since we are having place & routing constraints  in our board, we placed BALUN near to the LMX part.

    still If we place the BALUN near to the ADC, the single ended clock from LMX length will be increased to 3 inches and this will effect the clock signal integrity issues. 

    Please provide the clarification.

    Thanks & regards,

    Divya

  • 0 in reply to Divya Jyothi1
    TI__Mastermind 41980 points

    Hi Divya,

    I apologize for the delay. Neeraj was covering for me while I was out of the office.

    I understand you have some brd layout design constraints and the balun is placed near the LMX part.

    My recommendation, is the placement is fine. However, the differential outputs of the balun connected to the ADC need to adhere to the differential constraints in order to get the added benefit of common mode noise cancellation. I would also make sure the output current of the LMX part is maximized in order to achieve the best/largest output Vpp swing and therefore slew of the clock. This will help with overcoming the loss of the balun and longer trace lengths before the clock signals get to the ADC.

    Lastly, I would definitely put a differential 100ohm resistor termination before the AC coupling caps and place all those components near the ADC clock input pins. 

    Regards,

    Rob