Data on DOUTx are shifted out on rising edge of DCLK but on page 17 the datasheet states "Data are shifted out on the falling edge of DCLK." and the timing diagram "Figure 1. Serial Interface Timing" on page 6 also.
But when I measure the signals directly at the DDC316 with a logic analyser the traces show me that data on DOUTx are shifted out on the falling edge of DCLK (e.g. see cursor A).
What's going on there?