ADS1287: ADS1287 Clocking with 0.1ppm/year oscillator

Hi Lorand,

Welcome to the TI E2E Forums!

If you are planning to run the ADS1287 in continuous-sync mode then I would recommend deriving the SYNC clock from the master clock so that these signals remain synchronous. In continuous-sync mode, the SYNC clock's rising edge must occur within a specific CLK period or else the ADC will resynchronize and require ~63 conversion periods for the FIR filter to settle (or 5 conversion periods when using only the SINC filter).

If occasional resynchronizing is not an issue, then you could probably get away with using separate clock sources. However, you'd still want to take care to satisfy the td(CLSY) timing requirement, which requires that the rising edges of SYNC and CLK not occur within 30 ns of each other. When using asynchronous clocks, this might require the use of a negative-edge triggered d-flip flop to reclock the rising-edge of the SYNC signal to the falling-edge of CLK.

Using a clock counter to divide the SYNC signal would be my recommendation. You can set the "divide-by-N" ratio so that the SYNC clock is triggered after a specified number of clock periods, in order to prevent resynchronization if the SYNC clock were to drift with respect to the CLK signal. To meet the td(CLSY) timing requirement with a clock counter, you'd could add some capacitance to the output of the clock counter to ensure that the propagation delay is at least 30 ns OR you could invert one of the clock signals to align the SYNC rising edge to the falling edge of CLK.

Regarding your specific questions...

Lorand Kertesz said:

1) would a 1MHz clock instead of the 1.024MHz one result in a 976SPS instead of the set 1KSPS?

Correct. The output data rate scales proportionally with the input clock. All of the specified data rates in the datasheet are assuming the nominal 1.024 MHz clock.

Lorand Kertesz said:

2) If I divide my 10MHz down to 1KHz and use that to continuously sync the ADCs while using a 40ppm 1.024MHz oscillator, would this get me a good sampling jitter? I mean if I connect a low jitter clock to the SYNC input, will I get the SNR I'd be expecting or the SYNC input does add a significant jitter to it?

 Internally, the the CLK signal is what drives the sampling rate, and the SYNC signal is latched on the rising edge of clock, so having a low jitter SYNC clock will not be of much benefit. You'll want the CLK signal to be low jitter to maintain high SNR. Since you're working with relatively low data rates, anything less than 1 ns standard deviation for clock jitter should be fine).

Lorand Kertesz said:

3) Any recommendations on how to divide the 10MHz down to 1kHz and get a clean clock? Could use a simple counter, like the CD74HC4059M96 but maybe there's a better solution.

I assume you mean 1 MHz for the CLK signal...I think when dividing down a clock signal you'll generally have lower phase noise. Also, with the low data rates of the ADS1282 and the high oversampling ration (i.e. you aren't measuring high-frequency signals that change significantly over a period of a couple of clock cycles and you're averaging many samples over time) the SNR will not be affected much so long as jitter is not excessive.

The CD74HC4059M96 appears to output a 1 clock period pulse after the counter is triggered. This device would probably work well for dividing the CLK signal down and generating the SYNC pulse. NOTE: Keep in mind that the SYNC high pulse for the ADS1287 needs to be at least 2 CLK periods, so you might need a flip-flop to provide at least a CLK/2 (or higher divider ratio) signal to the LE to keep the SYNC pin high for tw(SYH).

For CLK you'll probably need a clock divider, or else some combination of a counter + latch to change and hold the clock state until the counter is triggered again. Perhaps there is something from this list or the CDCE906 which would be suitable. Clock dividers are not my area of expertise, so you might ask the question in the E2E Logic Forum to see if someone there with more expertise could provide more guidance on clock dividers. 

I hope that helps!