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Original question:

DDC316: Data on DOUTx are shifted out on rising edge of DCLK, why?

DDC316: Problem with overflow detection (>=100% Fullscale input signal)

Bernhard Gaus
Prodigy 50 points
Part Number: DDC316

The data sheet of the DDC316 states (page 12 table 2) that input signals >=100% FSR will result in ideal output code 0xFFFF.

If an input is supplied with a current that slightly exceeds >=100%FSR the output code is 0xFFFF.

But if the input current further rises to higher values e.g. >120%FSR the output code lowers to values < 0xFFFF.

This behaviour doesn't allow to precisely detect an overflow condition.

Is there any other possibility to detect the overflow?

Regards,

Bernhard

  • 0
    TI__Expert 4630 points

    Hi Bernhard,

    That is strange. If you overflow the input, there will be some saturation effects, with the input voltage rising (beyond zero) potentially affecting the next samples when signal gets into range or adjacent channels, but I think you should still be getting all ones. Can you describe a bit your setup?

    Regards,
    Edu