ADS8568: Interfacing ADS8568 with DSP by UPP terminals

Hi Ray,

I am not an expert on the EMIF of the TMS320C6657, but I am familiar with the operation of the ADS8568. Let me explain the basics of the converter interface and perhaps Bill or one of the DSP experts can pick up on the EMIF specifics from there.

Please refer to Figures 2 and 3 in the ADS8568 datasheet - there are a couple different aspects to the control of the ADC.  First and foremost is the application of the CONVST (convert start) input to the device.  There are four CONVST inputs to the ADS8568 and each one controls a channel pair of ADC's within the chip.  The most common way to use the ADS8568 is to tie all of the CONVST inputs together and use a single strobe to get 8 channels of data simultaneously sampled.  CONVST is an asynchronous input and could be driven by a timer, a PWM a GPIO or some external system level event.

Once CONVST is applied, there is an output signal called BUSY which indicates that the converter is doing its job.  This output will go high at the start of the conversion and then drive low ~1.7uS later indicating that the conversion has completed.  BUSY is usually connected to an interrupt pin.  The falling edge of BUSY would initiate a data transfer to the EMIF.  Assuming you have all eight channels of the ADS8568 enabled, the EMIF would need to set the /CS pin of the ADS8568 low, and then strobe the /RD pin to put the 16-bit data of the conversion results onto the parallel data bus.  By Figure 2, the /CS could be held low while strobing /RD eight times, or the /CS could toggle with each /RD as long as the setup and hold times are met.  Please note - you might need an external 'address decoder' to interface between the EMIF address bus and the ADS8568 /CS input.

Hi Ray,

Tom presents a good strategy.  If the convert and busy signals are connected as GPIOs, the busy could be used to initiate a transfer using the EMIF interface.  The EMIF provides a programmable delay for the CS and RD or WR signals allowing the timing to match the specification in the ADS85568.  Accesses could be done using individual reads or as a DMA burst.  The address would increment during accesses but that isn't needed for the ADS85568.  For more information on programming the interface timing see the External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A).

Regards, Bill