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AMC1306M25: Interpretation of DOUT in Figure 53 of datasheet when AVDD is missing

Part Number: AMC1306M25
Other Parts Discussed in Thread: AMC1306E25, AMC1306M05, , AMC1306E05

I want to understand what bit pattern to detect on DOUT for the failure scenarios below.
In the datasheet for AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25 SBAS734A –MARCH 2017–REVISED JULY 2017 section 8.4.1 describes in words that the output DOUT of the device offers a steady-state bitstream of logic 0's in case of a missing AVDD. It also describes if the common-mode voltage of the input reaches or exceeds the specified common-mode overvoltage detection level VCMov then a steady-state bitstream of logic 1's are output on DOUT. However, Figure 53 appears to suggest that a Test Pattern exists when AVDD is good. From the wording above I do not expect that pattern to be anything other than 1's, is that correct.
Also I don't know whether there is a way of knowing through DOUT when t ASTART starts which would be required as that determines when DOUT has a Valid Bit Stream.
What I intend to do is monitor for 128 or more consecutive 0's or 128 or more consecutive 1's and if either of these are detected then the Bit Stream in not Valid. To transition to a Valid Bit Stream requires DOUT to not have 128 consecutive '0's or not have 128 consecutive 1's. Is that the correct assumption?
Please advise

  • Hello Pav,

    The test pattern appears any time the device is powered up (when AVDD comes up to the correct value), and it will continue during the entire tISTART time period regardless of whether there is a fault on the Vcm. This tiSTART  test pattern will last for 32 clocks and is a series of alternating 1s and 0s. 

    Once the tiSTART period is complete, the VcmOV failsafe output could be output, so you will see all 1s after the tiSTART period is complete if the Vcm is still in an overvoltage state once the test pattern is done.

    Your assumption is correct. You can determine when tASTART begins through DOUT by looking for the transition from all 0s to some non-zero values. Since the full scale input will still show a pulse every 127 clock cycles, you can determine that the AVDD is down if the bistream shows all 0s for longer than 127 clock cycles. Once that is determined, you will know that tASTART has begun as soon as the bitstream transitions again to 1.

    Note that if there is an AVDD fault, and there are at least 128 consecutive 0s, the bitstream will not be valid again until 5ms after the first 1 is seen again.

    However, the bitstream is immediately valid as soon as there are no longer 128 consecutive 1s.


  • Hello Scott,

    Thanks for your prompt response.

    This has helped me to understand some of the contradictions with respect to the Fail-safe output on DOUT but there are two aspects of your response that I need further clarification on.

    1. With reference to '...the bitstream will not be valid again until 5ms after the first 1 is seen again...' should 5ms be 0.5 ms (TYP tASTART). If it is 5 ms where is that specified?

    2. With reference to 'However, the bitstream is immediately valid as soon as there are no longer 128 consecutive 1s.' I assume that this is because either AVDD was good but Vcm was in overvoltage state and as soon as Vcm moves out of that state DOUT is valid, or AVDD was missing and once AVDD recovers to start the initialisation sequence when that sequence completes Vcm could still be in the overvoltage state (i.e. the 1 shown on DOUT in Figure 53 in between Test Pattern and Bit Stream Not Valid), is that correct?



  • Hi Pav,

    1. You're correct, the tASTART is 0.5ms. That was simply a typo. 

    2. And yes, that is also correct. If the only fault is the Vcm in overvoltage, if the Vcm returns to a normal state the DOUT will have a valid bitstream immediately. The only time the bitstream will be invalid after a fault is removed is if the AVDD went down. Once AVDD comes back up the AMC1306 will need to go through its startup sequence which takes time equal to tASTART before the bitstream is valid again, regardless of other faults.

    Note that the failsafe output for the Vcm overvoltage could be output as early as the end of tISTART if the Vcm is in an overvoltage state after the AVDD has returned to normal. 


  • Hello Scott,

    Thanks, that's helped me to fully understand the Fail-safe output on DOUT.

    I would suggest that the description of the Test Pattern being alternating 1's and 0's are added to the next update of the datasheet to avoid any ambiguity regarding DOUT when AVDD is missing.