Hello, I am using a LMK 04828 along with a DAC38J82. An FPGA is transmitting ADC samples to the DAC and the LMK is providing all clocks. A few things about my board: Dclkout0_1 is for the Dac reference (1.2 GHz) and sysref, respectively. Dclkout6_7 is the FPGA serial tx reference (150 MHz)--no sysref. My line rate is 6 Gbps. The lmk and adc are working, but the dac has no output. The dac is receiving output as verified by both chipscope interally and a scope externally. The Dac pll and serdes pll are locking. The dac gives only one error flag: Fifo read empty. I have searched this forum and have learned that this can be from a mismatch in serdes line rates. My rates, as far as I can tell, match however; the fpga transmitter line rate was verified by o-scope. I cannot verify the DAC line rate, but I used the formula in the datasheet. Also, the dac sync does not respond to sysref pulses. In the following figures, the ending numbers in the names correspond to register addresses. Registers are programmed in ascending order; lmk first, dac is reset, dac registers programmed, jesd core is reset, then sysref pulse is triggered. Any help would be greatly appreciated. Thank you for your time.
My LMK Settings (register 101 is at the top of the far right panel):
Dac Settings:
