ADS41B49 datasheet issues.

Ralph Loader

Prodigy 70 points

Other Parts Discussed in Thread: ADS41B49

Hi,

I noticed a few issues in the ADS41B49 datasheet:

On page 6, it is stated that RESET, SCLK, SDATA, SEN support 3.3v, which contradicts the absolute max on page 2 (AVDD+0.3). I assume the absolute maximum is incorrect - referencing the digital pins to AVDD is a bit odd. [Also, should the absolute max for INP/INM be referenenced to AVDD_BUF not AVDD I wonder?]
On page 21, the default value of the register is given as 00h, but the text says the gain bits default to 0101 [which would make the default 50h, I think].
Page 47, 'corretion' should be 'correction'.
Page 27, 'bit EN OFFSET CORR must be set' is misleading - 'only applicable when EN OFFSET CORR set' would be more accurate.
Page 46, On CMOS v. LVDS clocks, the first paragraph ('little or no difference') appears to contradict the second ('For best performance ... must be driven differentially').

over 13 years ago

0 RJ Hopper over 13 years ago

TI__Mastermind 18095 points

Thanks. These issues will be addressed. --RJH

0 Ralph Loader over 13 years ago in reply to RJ Hopper

Prodigy 70 points

A couple of other minor issues:

On page 18, it reads as though a start up pulse on the reset pin is required in serial interface mode, but on the page 16 it is stated that the serial mode start-up reset can be done either via the reset pin or via the serial interface. I assume that the page 16 text is correct.

The OE pin is not listed in the abs. max ratings.

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ADS41B49 datasheet issues.