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Original question:

TLC5540: For (0-5V) ref voltage configuration, center the Analog input signal to 2.5V and swing of max +/- 2.5V

TLC5540: Latch / Buffer IC in between Data lines

Abhishek Kumar10
Prodigy 110 points
Part Number: TLC5540

In the datasheet of TLC5540IPW, it is mentioned that "It is recommended to place the digital output data latch (if used) as close to the TLC5540 as possible to minimize capacitive loading. If D0 through D7 must drive large capacitive loads, internal ADC noise may be experienced.", but no where it is mentioned that what is the drive strength which output Data bit pins can support?

We are planning to use TLC5540IPW in our design in which we will be connecting the D0-D7 bits to Xylinx FPGA "XC4010E", so could you please confirm whether we can directly connect the Data lines to FPGA or is it a must to have a buffer in between?

  • 0
    TI__Guru* 91947 points

    Abhishek,

    If you are operating the ADC at 40MHz, if the trace length between the ADC output data lines and the FPGA are longer than 4 inches, I would recommend using a buffer. If you are running the ADC slower, you may be able to get by with a little bit longer trace length.

    Regards,

    Jim   

  • 0 in reply to jim s
    Prodigy 110 points

    We would be operating ADC and FPGA both at 5MHz as the clock on the board is 5MHz being fed to both ADC and FPGA so with this working frequency could you please let us know what is the maximum length which can be allowed without using a buffer? I will go ahead without a buffer in my design based on your input.

  • +1 in reply to Abhishek Kumar10
    TI__Guru* 91947 points

    It really depends on the rise time of the signal. 10ps rise time on a 1kHz signal will cause reflections, but because of the period it’s probably not going to cause issues. 

    There are a couple rules of thumb out there that say any trace longer than 1/3rd or 1/6th the rise time will cause issues.   For this case, let’s use the 1/3rd rule as this seems to work for the RS-485 and other single-ended signals

    So if FR4 is used and the trace is ~180ps/inch and the max data rate is 5MHz, I would guesstimate the rise time on the order of 5-7ns and the trace length of the 1/3rd rule would be 9-13 inches.

    Slow rise time and longer trace lengths will require more drive strength.

    This is all pure speculation about the actual rise time of the CMOS output. Since this is a very old device and the drive strength and rise time information is missing from the data sheet, TI cannot guarantee this will work without the buffer at these trace lengths.