ADC12DJ5200RF: ADC12DJ5200:Fs/4±Fin and Fs/2-Fin have large interweaving spurs,is there any way to improve?

This is my own design.

 Configuration steps:

• Click on JESD Block Enable to stop the JESD204B block. (0x200=0x00)
• Navigate back to the Control tab and click on Enable Calibration Block to disable calibration and allow setting changes.(0x061=0x00)
• Click on Enable Foreground Cal and Foregroud Offset Cal.(0x062=0x05)
• Click on Enable Calibration Block to re-enable the calibration subsystem(0x061=0x01)
• click on JESD Block Enable to re-start the JESD204B block.(0x200=0x01)
• Navigate back to the Control tab and click the Cal Triggered/Running button once, then click it again. This restarts the Calibration engine. (0x06C=0x00,then 0x06C=0x01)

Power design block diagram：

HI，Thanks for your support

Hi Bai,

Can you please try JMODE3 instead of JMOD3 and report if the spurs are still too large.

Also can also read the register address 0x006 and report back the value.

Regards,

Neeraj

The register with address 0x006 does not appear in the data sheet, but we tried to read the register with address 0x006, and the return value is 0x02.

I found that when the sampling clock frequency becomes higher, whether it is in single-channel mode or dual-channel mode, the indicators will be significantly reduced. JMODE1-7GSPS (Fs=3.5GHz) is much better than JMODE3-5.2GSPS (Fs=5.2GHz). Whether the sampling clock input circuit needs attention.

When we test on ADC12DJ5200,other registers can be read and written normally, we try to adjust the value of register Bx_TIME_y, but the read value is still the default value（0x00） and cannot be modified; can we modify the register value of Bx_TIME_y？

When we test on ADC12DJ3200, the Bx_TIME_y register can be read and written normally.

HI Neeraj,

Thank you very much for your support.

When we test on ADC12DJ3200, we can read and write Bx_TIME_y register normally. Read the register whose address is 0X103, and the return value is 0X96. After collecting the data, analyze it as shown in the figure below.

When we test on ADC12DJ5200, we read the register whose address is 0X103, and the return value is 0X00. So we made a test, set the register address 0X103 on ADC12DJ3200, the value written is 0X00, and the data is collected and analyzed as shown in the figure below.

Through the above analysis, proper adjustment of Bx_TIME_y will improve the influence of Fs/4±Fin. I hope that ADC12DJ5200 can also allow users to modify the register value of Bx_TIME_y according to their own design. Will this function be available to customers in the future?

Regards,