ADS5270: ADS5270: VCM does not start up correctly

Hi,

I will be looking into this.   There is not any errata that in know of regarding the VCM output.  at present I do not see a clear reason for what you are describing.

since you are operating with internal voltage reference, and the VCM output is expected to be about midway between REFT and REFB, may I ask that you measure the voltages at REFT and REFB in case that provides any clue?

Also, if the analog inputs were AC coupled then we could measure the VCM of the signal at the analog input pins and see if the internal VCM biasing is still biasing the signal to about 1.45V or to the 0.6V.   Would it be possible to open up the series 56 ohm in the signal path temporarily to check the VCM of the analog input?

Also, I notice that the amps do not drive a load resistance after the series 56 ohm and before the ADC, so the amp will be driving a relatively high impedance of ~1200 ohms.  Is this desired?  Just wondering.

Regards,

Richard P.

Richard,

thanks for your fast reply. We will try to do the measurement without the 56 ohm series resistor and get back to you.

As for the high impedance: No special reason. The schematic is just as we've seen that in application notes.

Do you think we should reduce the impedance? By adding a resistor in parallel of the ADC input pins?

Regards,

Steven

Hi Richard,

maybe the following is is connected to our problem:

If we understand correctly:

Before the ADC starts up and drives the VCM pin with 1.45V this pin ist "tristated"

The differential apmlifier's VCM input pin is internaly held at VCC/2 using a weak resistor divider.
VCC/2 is 1.65V.

That means before the ADC's VCM output rises the common mode voltage applied to the analog input pins of the ADC is 200mV off the 1.45V reference voltage.

Would that be a problem?
Is there some kind of VCM protection circuit? Or some kind of monitoring the applied common mode voltage?

Regards,

Steven

Richard,

I did as you sugested and removed the 56 Ohm at one channel of the ADC:

VCC=3.187V
REFB=0.936V
REFT=1.931V
VCM=0.5V

At the open input pins I can measure 0.537V.
So it seems that the internal biasing is not working.

Steven

If the system powers up with the amp driving a little different VCM such as 1.65V instead of the 1.45V, that should be no problem.  with the analog input signal being outside the desired range of common mode voltage the performance specs of the ADC would not be guaranteed but since the ADC s not yet powered up anyway then this would not be a concern.   The analog input pins might be violating the absolute max specifications in the datasheet since there is a signal present on the input pins before the power is applied to the ADC, and the ESD protection diodes in the ADC might be turned on, but if the amp is not able to source a nearly unlimited amount of current into the ADC input pins then a short period of the amp powering up before the ADC should not shorten the life of the ADC appreciably.   If the ADC has its power supplies present but the ADC is in an internal 'powerdown' state, then even the abs max limits would not be violated if the amp were up and running and sourcing its output at a VCM of about 1.65V.

I will ask the design team for this device if there is any reason why the VCM output should be doing what you are seeing. It is beginning to sound like there are some faulty devices and we may ask for some of them to be returned for failure analysis.  possibly the devices have been damaged.  I will check with the design team.

You are providing a reset pulse to the ADC, correct?  May I ask what you are programming into the SPI configuration registers?

Regards,

Richard P.

Richard,

the op amps and the ADC are powered by the same supply, thus starting up at the same time. What I meant was that apparently the VCM output of the ADC starts later.

The reset pin of the ADC is controlled by an FPGA. But this happens several hundred milliseconds later since the loading and starup of the FPGA takes soem time.

As I understand the datasheet the reset input only resets the LVDS and the logic part of the ADC. Is the generation of VCM connected to the reset?

After powering and starting up the FPGA sends three commands to the ADC. First 

"00000100"; -- ADC SPI command for deskew pattern (bit sync) and
"00001000"; -- ADC SPI command for sync pattern (word sync)

are used to synchronise the FPGA LVDS logic to the ADC. Then 

"00000000"; -- ADC SPI command for normal operation

is sent. That's all.

Regards,

Steven

Richard,

It seems that the ADC startup problems began when we replaced the Diff OpAmp LMH6651 with the newer THS4531 to reduce power consumption.

(See links for datasheets).

How could that be?

I further noticed that some of our ADC output 1.50V instead of 1.45V on the VCM pin even if all analog inputs are left unconnected.

Looking forward to your reply.

Thanks!

Steven

Hi,

I went back and reviewed all of the prior material.  So the circuit that was in the original pdf attachment with the LMH6551 was actually a design that did not exhibit the issue?  And that just changing the amp in the data path from the LMH6551 to the THS4531 was when the issue was seen?  did the supply rails to the newer amp change at the same time?

Usually the datasheet for the amp will have a current spec for the common mode control input pin and that is usually in terms of microvolts.  And the ADC will usually have current capability of a few milliamps.  But in the amp datasheet this current spec seems to be a bit of a simplification depending on the supply voltages and the actual VCM.  But looking at the two datasheets more closely, I see the common mode biasing is a bit different but not in a manner that I would expect to cause an issue.  For example, one has biasing resistors of 50Kohm instead of 60Kohm.  But if one design has supplies of +5V to -5V and the other design didn't, then the current draw could be somewhat different.   Still not such that I would expect to see much difference though.    What is more of an unknown to me is that other amp device used to buffer the VCM from the ADC to the 8 amps in the data paths.  In the original design that amp had the same supplies and the LMH6551.   That is another reason I wanted to ask if the supplies are still the same for the THS6551 design.   also - if the buffer were removed and the input shunted through to the output to let the ADC supply VCM to all 8 channels - does that clear up the issue?  It looks like the ADC current capabilities should be enough for that, although I would have considered buffering VCM as well.

Regards,

Richard P