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Original question:

ADC32RF45: ADC32RF45

ADC32RF45: how to calculate lane rate for Byapss mode LMFS=8224 and adc fs is 2500MHZ

Ravindra Reddy
Prodigy 80 points
Part Number: ADC32RF45
Other Parts Discussed in Thread: LMK04828

how to calculate Lane rate for the Bypass mode of LMFS=8224 mode

ADC frequency is 2500MHZ, SYSREF is 2.4414062MHZ, No of Lane is 8.

  • 0
    TI__Genius 10505 points

    Hi Ravindra,

    As shown in table 14 of ADC32RF45 datasheet, RATIO [fSerDes / fCLK (Gbps / GSPS)] for this mode is 5. So lane rate is 5*2.5 = 12.5 Gbps.

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 80 points

    Thank you varma,

    The lane rate what is given in table 14 of ADC32RF45 datasheet is [fSerDes / fCLK (12.5gbps), but this lane rate is lane per lane is 12.5gbps or 8 lanes rate is 12.5gbps (12.5/8 is 1.5625gbps per lane).

    i am using jesd204b xilinx ip in that it is asking to set lane rate. Is I need to mention lane rate is 12.5gbps or 1.5625gbps??. Please reply as soon as possible.

  • 0 in reply to Ravindra Reddy
    TI__Genius 10505 points

    Hi Ravindra,

    'Lane rate' generally means bit rate per lane. That's how it's mentioned in the ADC datasheet in table 14. It's 12.5Gbps per each lane. Total bit rate of from all 8 lanes combined is 12.5*8 = 100Gbps. 

    If Xilinx IP asks for lane rate, I think it should be set to 12.5Gbps. I assume number of lanes is separately entered in configuration. 

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 80 points

    Thank you Varma,

    Lane rate issue was resolved. In ADC32RF45 datasheet few registers are mentioned but where the configuration GUI is given more registers for ADC configuration which are not present in datasheet. Please provide complete registers set related information for ADC32RF45.

  • 0 in reply to Ravindra Reddy
    TI__Genius 10505 points

    Hi Ravindra,

    For ADC configuration from hardware reset, many analog trim registers need to be configured. This configuration is fixed for all modes. These registers are internal to TI and not described in the documentation. All digital registers (which are relevant to customers) are described in the datasheet.  

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 80 points

    Thank you,

    I configured the ADC32RF45 for fs=2500mhz and bypass mode 8224(lane rate is 12.5gbps). And I calculated  the SYSREF (fs/LMFC) i.e. 2500/1024=2.44140625mhz. is any other SYSREF frequency value to be used for better performance?. 

  • 0 in reply to Ravindra Reddy
    TI__Genius 10505 points

    Hi Ravindra,

    As shown in Table 2 in www.ti.com/.../sbaa221.pdf,

    for 8224 mode, SYSREF should be fS / LCM(64, 4 × K)/N and N can be selected such that SYSREF frequency is less than 5 MHz. 

    The frequency you selected satisfies these conditions. It will give best possible performance. Also SYSREF can be turned off after initial bringup to avoid on-board coupling to critical RF signals like ADC input and clock. 

    Regards,

    Vijay

  • 0 in reply to Vijayendra Varma Siddamsetty
    Prodigy 80 points

    Thank you vijay for good support, 

    I working on ADC32RF45 (bypass mode-8224, fs=2500mhz) and interfaced to Xilinx jesd204b IP. I got continues Lane errors at jesd204b IP receiver. 

    I used LMK04828 for clocking the ADC and JESD204B IP.  In LMK04828 I configured all clock output type to LVDS. And clock output type is LVDS is ok? or I need to select another Types Like HSDS or LVPECL.

    Which Type of  clock output format is need to give to ADC(LVDS or LVPECL or HSDS)?. 

    Similarly Clock output Formats for, 

    SYSREF and JESD204B IP clocks?

  • 0 in reply to Ravindra Reddy
    TI__Genius 10505 points

    Hi Ravindra,

    On the EVM, I see that LMK output format for FPGA ref clock (JESD IP clock) and SYSREF is LVDS.

    For ADC clock input, LVPECL 2000 mV format is used. This is AC coupled on the EVM. This format is used to get maximum differential swing from LMK. 

    For ADC SYSREF, LVDS is used. 

    Please verify that ADC clock is AC coupled and try with LVPECL 2000 mV format for ADC clock. 

    Regards,

    Vijay