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DLPLCRC410EVM: DLP7000

Charlie Ouyang
Prodigy 10 points
Part Number: DLPLCRC410EVM
Other Parts Discussed in Thread: DLP7000, DLPC410

Hi team,

I have got one DLP4100 development platform and one DLP7000 module. I have already successfully connected the system and powered on board. Everything is working normally in default program.  I also successfully connected it to the windows application ‘Discovery 4100 Explorer’.

I need your support on the next step action about the pixel level control method.

My requirement is:

-I just used certain block. E.g. : 7.

-I want control some pixels on block 7 to switching at certain frequency(1KHz, 10KHz or 20KHz). Is there any reference script available. Or I have to modify the APP controller code.

Thanks.

Charlie

  • 0
    TI__Mastermind 46660 points

    Hello Charlie,

    The speed is possible, but not over USB using the GUI or external scrip.  You will have to modify the APPS_FPGA code.  If the patterns can be programmatically generated, then this can be done in the APPS_FPGA.  If not, you will be able to store about 7-8 blocks worth of pattern in the memory of the current APPS_FPGA design.

    If you wish to only address only some lines in the block, then more could be stored.  This would have to be determined by trying it.

    Fizix

  • 0 in reply to Fizix
    Prodigy 10 points

    Hello Fizix,

    Your suggestion is helpful. Before I move to the APPFPGA code, I want to know if I can do some tests based on GUI over USB.

    Can I do pixel control on GUI with a low switching speed? If yes, is there any sample script?

    Thanks.

    Charlie

  • 0 in reply to Charlie Ouyang
    TI__Mastermind 46660 points

    Hello Charlie,

    You can use the GUI for low speed testing.  However, the GUI itself only understands a full pattern, but you can load only the block you need.

    The GUI cannot do individual line loads.

    To make it work build a full XGA pattern, with the information you want in block 7 and similarly for each different pattern you want in block 7.  Then in the GUI have it load and reset only block 7.  Do this for as many patterns as you need in block 7.

    When you do this from the Apps you will be able to load only the rows you need.

    Fizix

  • 0 in reply to Fizix
    Prodigy 10 points

    Fizix,

    sorry for the wrong typing with my bad internet connection. Does Ti provide any tool for building a XGA pattern. Thanks for your patience.

    Charlie

  • 0 in reply to Charlie Ouyang
    TI__Mastermind 46660 points

    Charlie,

    Unfortunately TI does not provide such a program.  You can start with any XGA image and use Paint.  If you wish to generate it programmatically, you can use Python, Labview, etc . . . to open and manipulate the images.

    Fizix

  • 0 in reply to Fizix
    Prodigy 10 points

    Thanks Fizix.

    Which file or guide need I read for developing the customized application on 410EVM?

  • 0 in reply to Charlie Ouyang
    TI__Expert 3700 points

    Hello Charlie,

    I am covering for Fizix today.

    Have you reviewed the software section of the user's guide? It is section 3 at the following link: https://www.ti.com/lit/pdf/dlpu040

    There are a number of script examples in there if you want to build customized sequences.

    Regards,

    Matt

  • 0 in reply to Charlie Ouyang
    TI__Mastermind 46660 points

    Charlie,

    For further clarity in what you are attempting to do in a customized application for the 410EVM, are you wanting to make your own customized APPS_FPGA code to run in the APPS_FPGA?  This sounds like what you are wanting to do.

    There is a the APPS_FPGA code from the previous version of the default pattern generator on this:

    https://www.ti.com/tool/DLPLCRC410EVM -  the bottom 3 items are various versions of the APPS _FPGA code.

    They show how to load and other operations from the FPGA.

    Let me know if this is what you are looking for.

    Fizix

  • 0 in reply to Matt Soucek
    Prodigy 10 points

    Hello Matt,

    I have read the guide but it has little information about how to develop the APPS FPGA.

    Thanks.

    Charlie

  • 0 in reply to Fizix
    Prodigy 10 points

    Hi Fizix,

    we have downloaded the demo code. But the software guy said he cannot compile the file successfully. Is there a complete software project for reference?

    Thanks. 

    Charlie

  • 0 in reply to Charlie Ouyang
    TI__Mastermind 46660 points

    Charlie,

    I am not aware of any further code from the demo package that is online.

    Is there an error that is being reported when compiling?

    Fizix

  • 0 in reply to Fizix
    Prodigy 10 points

    Fizix,

    Does TI support develop the module of DLP7000 by customer theirselves with their own FPGA chips? I mean that IT can share the protocals and register setting user manual to us.

    THanks.

    Charlie

  • 0 in reply to Charlie Ouyang
    TI__Expert 3700 points

    Hi Charles, 

    We have a fair amount of HW and SW information on our ti.com website. The goal of the Applications FPGA Design files, programmer's guides, and GUI is for customers to get their systems going quickly, and then to have them develop new code or work with design houses to meet the requirements for their products. 

    The listing of the evaluation module items can be found here.

    https://www.ti.com/tool/DLPLCR70EVM

    Is there more information you are looking for?

    Regards,

    Matt

  • 0 in reply to Matt Soucek
    Prodigy 10 points

    Thank you, matt. 

    What is the maximum frame rate could be achievd by Discovery 4100 Explorer with DLP7000? Per my test results, load and display a frame on DLP7000 will spend about 102ms.

    I aslo want to confirm if TI support develop the module of DLP7000 by customer theirselves with their own FPGA chips? I mean that IT can share the protocals and register setting user manual of DLP7000 to us.

    Regards,

    Charlie

  • 0 in reply to Charlie Ouyang
    TI__Mastermind 46660 points

    Hello again Charilie,

    So we are clear, are you talking about a 24-bit color frame or one 1-bit pattern.  With global micro-mirror resets, with careful APPS_FPGA design you can reach fairly close to the DMD limit which is around 23 kbpps (binary patterns per second).  It is possible to go a bit faster with phased resets - around 32 kbpps.  NOTE:  Phased reset is analogous to the scrolling shutter operation in a cell phone camera.

    This will depend also on how you design your input system.  Are you going to generate patterns algorithmically in the APPS_FPGA or are you going to design an external input system through the EXP connectors?

    Fizix

  • 0 in reply to Charlie Ouyang
    TI__Mastermind 46660 points

    Charlie,

    I wanted to add that there are some parts of the protocols that are between the controller and DMD.  Since we require that the DMD be operated with the controller, we do not share the protocols between the controller and DMD.  

    The DLPC410 is designed so that all communication to a user FPGA is done through signals and not registers.  All the necessary information should be in the data sheet.  

    Fizix