DLP660TE: DMD displays checkerboard pattern while in projection mode: external

Florian -

I don't see any link or reference to the "similar problem" or "related question".  Can you provide a link to the issue you are referring to, or describe the problem?

Thanks,
Gary

Hello Gary, 

here is a link to the related question. 

https://e2e.ti.com/support/dlp-products-group/dlp/f/dlp-products-forum/952213/dlp660te-checkboard-pattern-and-vx1-video-input

Best Regards,

Florian

Florian,

Can you confirm what versions of ASIC and FPGA firmware images are you running on the EVMs? You can find the ASIC firmware version under System and the FPGA firmware under FPGA Control.

I would assume that you already loaded the ASIC and FPGA firmware that is provided with the firmware download from https://www.ti.com/tool/DLP660TE-SW. If that is not the case then please do so. ASIC firmware programming instructions can be found in the DLPLCRDC4422EVM User's Guide and the FPGA firmware programming instructions can be found in the directory created during firmware package installation (see below).

ASIC firmware version:

FPGA Firmware: 

We downloaded and installed the firmware for the dlp660 provided by ti.com. Above you can find screenshots from our GUI. 

Regards, 

Florian

Florian,

We have tried to duplicate your findings with our setup and are not able to do so. Unfortunately we're not able to debug specific issues with Vx1 front ends that we haven't worked with,  If you're working on designing a projector for production send me a friend request so that we can discuss offline on the best channels to get you setup.

Regards,

Mike

Our current goal with the dmd is not related to any projector work. We are just trying to use the dmd to display a binary pattern. 

Do you have any suggestions on where the problem may lie? Since we get part of our videosignal displayed on the dmd, this should not be a Vx1 frontend problem or am I getting something wrong here?

Regards,

Florian

Florian,

I have sent you a friend request so that we can look into options offline.

Mike, 

It seems like we are not the only customer with this kind of problem and turninig this discussion into an offline chat, would not benefit anyone of them. I would much rather keep this discussion online to also help others. 

Do you have any other suggestions on how to resolve this issue?

Regards,

Florian.

Florian,

Are you using one of the specific timings supported w/ Vx1 pixel clock @ 600MHz?  The supported timings are listed in an xls file included in the DLP660TE firmware and GUI package.

Regards,
Gary

Gary, 

we are currently using the settings row 8, but we also tried using row 7 with no difference in  outcome. 

Regards,

Florian

Florian,

There are 3 LEDs that might be somewhat helpful in maybe figuring out what is going on:

• D10 (Green) – FPGA Config Done
  • Indicates FPGA is configured (bitstream is loaded)
• D1 (Green) – Vby1 Locked
• D2 (Green) – Vby1 Hot Plug Detect

What is the status of these LEDs on your system when sending Vx1 data to the FPGA?

Thanks,
Gary

Gary, 

D10 is on (green)

D1 is off

D2 is on (green) 

Regards,

Florian

Florian,

Thanks.  So, it seems the FPGA is configured (D10 is on), and there is a Vby1 Hot Plug Detect.  For whatever reason, the Vby1 is not locking.

All of the rates in the table have been tested.  I cannot recall if this is necessary to get a lock... but can you make sure the "XPR OFF 2WAY" is selected in the DLPC4422 GUI -> Projector Control -> FPGA Control...

Does that change anything for D1 (Vby1 Locked LED)?

Thanks,

Gary

Hello Gary, 

thanks for your suggestion. Unfortunately, it did not change anything about the D1 LED status or the dmd image. 

Regards,

Florian