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DLPLIGHTCRAFTER: DLPLCR9000EVM

Yujie Shen
Prodigy 45 points

Part Number: DLPLIGHTCRAFTER

Hi Team

  We have this DLPCR9000EVM evaluation board currently in the group, and I'm testing it to confirm certain characteristics so we could later proceed with the correct model for our application. To get a better knowledge on DMDs, I'd like to inquire some basic info regarding this module (and possibly the DLP9000 chip):

1. So from the 101 document, if I use a global reset, there will be a reset period during which all the micromirrors on the chip will change to its new state. So where can I find this parameter for the DLP9000 chip? I only saw a 'cross-over' time of 2.5us in the spec sheet, but I suppose that's not the actual reset time? Also, during the reset period, does all the mirrors change states simultaneously, or it's actually done in a 'rolling-shutter-fashion' so some micromirrors change first and others later?

2. And when I use the 'pattern on the fly' mode in GUI, it kept reminding me that the dark time should be more than 105us --- so what exactly is this dark time? is it the time to load the CMOS cells plus the reset period? Oh and a related question: the LVDS to this chip is 32-bit like in the 101 document (so updating one row takes 80 clock pulses)?

3. Is it possible to only load and update a subset of the chip in each block? Also I recall Fizix once told me that DLP650LNIR could do this Load4 operation so effectively reducing the load time (I only need to load same patterns across multiple rows in a block), just wondering if it is possible with the DLP9000 chip? And maybe even through the GUI?

4. One last question: I'm curious if it is possible to get larger flash memory on the DLP chip? The DLPCR9000EVM seems to be able to store up to 400 binary patterns, but we might need something up to 1600 patterns.

Thanks,

  Yujie Shen

  • 0
    TI__Expert 3675 points

    Hi Yujie,

    Welcome to the TI E2E forum and thank you for your interest in DLP technology!

    One of our experts will soon get back to you.

    Thanks,
    Akhil

  • +1
    TI__Mastermind 45415 points

    Hello Yujie,

    Apparently this post was originally mis-assigned.  I will help you with the inquiry.

    The original 101 document that you refer to was written some time ago (by me).  We now have many DMDs with various pixel designs.  The DLPC900 controller also operates a little different from the 4100 controller.

    Here are your questions:

    1. So from the 101 document, if I use a global reset, there will be a reset period during which all the micromirrors on the chip will change to its new state. So where can I find this parameter for the DLP9000 chip? I only saw a 'cross-over' time of 2.5us in the spec sheet, but I suppose that's not the actual reset time? Also, during the reset period, does all the mirrors change states simultaneously, or it's actually done in a 'rolling-shutter-fashion' so some micromirrors change first and others later?

    The DLPC900 only comprehends "global" resets.  The 2.5 us is the 'cross-over' time in which the mirrors that change state (on->off or off->on) take to reach the other side.  There is also some settling time, but the controller takes care of this.  This DMD has the "reset" (mirror clocking pulse) circuitry inside the DMD, and therefore the reset blocks are staggered very slightly to reduce the power draw.  This is very short in duration and is still effectively global.

    2. And when I use the 'pattern on the fly' mode in GUI, it kept reminding me that the dark time should be more than 105us --- so what exactly is this dark time? is it the time to load the CMOS cells plus the reset period? Oh and a related question: the LVDS to this chip is 32-bit like in the 101 document (so updating one row takes 80 clock pulses)?

    The base load and reset time for this DMD array is 105 us.  To have "dark" time defined in Pattern On-the-Fly Mode it must load 0's, that is why it must be 105 us or longer.  

    Regarding the LVDS interface, this DMD has a 64-bit interface and the row cycle is 20 clocks long (40 clock edges).

    3. Is it possible to only load and update a subset of the chip in each block? Also I recall Fizix once told me that DLP650LNIR could do this Load4 operation so effectively reducing the load time (I only need to load same patterns across multiple rows in a block), just wondering if it is possible with the DLP9000 chip? And maybe even through the GUI?

    Load 4 is not available for the DLPC900/DLP9000 chipset.  It can be done with the DLPC910/DLP9000X chipset.  The DLPC910 also allows random row addressing.

    The  DLPC900/DLP9000 chipset does allow you to set the active blocks.  They must be in a single contiguous range of blocks - i.e. you can set a start block and an end block.  This is controlled in the GUI under the Pattern Mode/Pattern Settings window.

    4. One last question: I'm curious if it is possible to get larger flash memory on the DLP chip? The DLPCR9000EVM seems to be able to store up to 400 binary patterns, but we might need something up to 1600 patterns.

    The newer EVM spins (when they become available) will have a larger flash on them and can hold many more patterns.  However only 400 1-bit patterns at a time can be loaded into the DLPC900 DDR pattern buffer memory.  This is a limitation of the controller, not the flash memory.

    If multiple sets of 400 1-bit images are loaded into the flash, to switch to another 400 1-bit patterns will require stopping the sequence and loading the next 400 1-bit patterns from flash and then starting the sequence running.  This is very much faster than loading patterns over the USB interface, but it is not continuous.  Somewhere around a second.

    The other method is to design a front end that packs the patterns into a video stream in real time and use Video Pattern Mode to display them "continuously".

    Fizix

  • 0 in reply to Fizix
    Prodigy 45 points

    Hi Fizix

      Good to hear from you, and thanks for replying! In this sense the evaluation board we have currently might not achieve our desired working condition. We thought we might just test the reset time ourselves using high speed photodiodes, and I could update on that later once I have some results. There are a few other questions I'd like to inquire, hope you won't mind switching gear to other modules and chipsets:

    1. I recall in the other thread we discussed about DLP650LNIR and if I use Load4 to only update 8 rows per block I could effectively go up to ~40kHz update rate. Just want to confirm that the actual hardware I will need to achieve this would be DLPLCR65NEVM and DLPLCRC410EVM? Also how many 1-bit images could I load into flash with this evaluation board? Shall I wait for a newer version of EVM to be able to hold more patterns (if so, about how far in the future)?

    2. We are also considering those automotive rating chips like DLP5531A-Q1 because they have a diamond pixel layout and the optical design would be easier for us. In the datasheet I only saw a refresh rate up to 10kHz --- does this mean a 1-bit pattern update rate of 10kHz? Could I also do Load4 of a few rows each block to boost this beyond 25kHz? The evaluation module DLP5531LEQ1EVM seems to be designed for some projection application, but I'm wondering if I could just use that as a spatial light modulator like the lightcrafter modules?

    Thanks,

      Yujie

  • 0 in reply to Yujie Shen
    TI__Mastermind 45415 points

    Hello again Yujie,

    You asked:

    1. I recall in the other thread we discussed about DLP650LNIR and if I use Load4 to only update 8 rows per block I could effectively go up to ~40kHz update rate. Just want to confirm that the actual hardware I will need to achieve this would be DLPLCR65NEVM and DLPLCRC410EVM? Also how many 1-bit images could I load into flash with this evaluation board? Shall I wait for a newer version of EVM to be able to hold more patterns (if so, about how far in the future)?

    Here is the main difference from the DLPC900 EVM.  There is no native memory on the DLPC410EVM.  There is a SODIMM memory slot on the board.  However you will need to program the APPS_FPGA yourself to have a memory interface and manage patterns and pattern data in the memory.  There is also an EXP interface that could be set up to transfer the patterns or you could preload them into the memory interface you design over USB, although it is not USB 3.0

    You are correct that for the DLP650LNIR the DLPLCR65NEVM is the correct DMD board to match with the DLPLCRC410EVM.

    2. We are also considering those automotive rating chips like DLP5531A-Q1 because they have a diamond pixel layout and the optical design would be easier for us. In the datasheet I only saw a refresh rate up to 10kHz --- does this mean a 1-bit pattern update rate of 10kHz? Could I also do Load4 of a few rows each block to boost this beyond 25kHz? The evaluation module DLP5531LEQ1EVM seems to be designed for some projection application, but I'm wondering if I could just use that as a spatial light modulator like the lightcrafter modules?

    I will have to have one of the team more familiar with the automotive chipsets respond to this question.  I will notify them.  I do not think the automotive chipsets support Load 4 functionality.

    Fizix

  • 0 in reply to Fizix
    Prodigy 45 points

    Hi Fizix

      Thanks. So am I understanding it correctly that I will need to install some memory on DLPC410EVM (like RAM on PC) to hold the patterns? I suppose it would be relatively easy to get a compatible memory board to hold 1600 patterns? But also data transfer between the memory board and the DMD chip would not be a bottleneck to the refresh rate, right?

      I'll wait for your colleague to reply on the automotive chips then. I guess I don't necessarily need to use Load4, but just random row access to address 8 rows in each block. If that could exceed 25kHz then it would work for us.

    Thanks,

      Yujie 

  • 0 in reply to Fizix
    TI__Intellectual 2325 points

    2. We are also considering those automotive rating chips like DLP5531A-Q1 because they have a diamond pixel layout and the optical design would be easier for us. In the datasheet I only saw a refresh rate up to 10kHz --- does this mean a 1-bit pattern update rate of 10kHz? Could I also do Load4 of a few rows each block to boost this beyond 25kHz? The evaluation module DLP5531LEQ1EVM seems to be designed for some projection application, but I'm wondering if I could just use that as a spatial light modulator like the lightcrafter.

     

    Yujie, Currently, the EVM for the DLP5531A-Q1 is design to supply support automotive headlight application and uses normal "video" type processing.    There are not modes defined to directly support high refresh rates.  It is limited to ~600Hz type of operation for single color input.  However, what type of applications would be suitable for the DLP5531A-Q1 type of DMD?  Do you need NIR window coating?

  • 0 in reply to Yujie Shen
    TI__Mastermind 45415 points

    Hello again Yujie,

    You asked:

    I suppose it would be relatively easy to get a compatible memory board to hold 1600 patterns?

    This is true, however be aware that this is a little bit older memory and can be a bit more expensive.  We have design partners like ViALUX, WinTech, and Dli that have modules that already have memory and their own proprietary software to do this.  I do not know if they can support partial loads, but you may want to check them out.

    But also data transfer between the memory board and the DMD chip would not be a bottleneck to the refresh rate, right?

    This is true if the memory controller is implemented correctly.  Note that TI does not have any examples of how to do this, it would be up to your FPGA programming partner.

    Fizix

  • 0 in reply to Jason Thompson
    Prodigy 45 points

    Hi Jason

      Thanks for replying. Yes NIR coated window would be best. Our application involves scanning a NIR laser spot across the DMD and use the pixels as fast on-off switch. Some key specs include: 

    1. Refresh rate up to 24kHz. But note that we only need a discrete number of rows (about 8 rows in each block)--- so if we could use random row addressing and even load4 mode I believe it should be achievable. Just not sure if we could get an evaluation board for this chipset to do this.

    2. Short switching time. Probably something similar to DLP650LNIR or DLP9000 would suffice (I still need to test).

    3. We'll definitely more than 400 pre-stored patterns (maybe up to 21 thousands 1-bit patterns). I am not sure about the memory requirement there. Also, will using external flash affect the pattern refresh rate?

    Please let me know your thoughts on this. If TI or some third party vendor could help configure such a board for us using the DLP5532-Q1 chipset that would be great.

    Thanks,

      Yujie

  • 0 in reply to Yujie Shen
    TI__Intellectual 2325 points

    Yujie,

    Thanks for the comments as we continued to evaluate new possible components solutions.  At this moment, we do not have a clear plan yet to develop a .55 chip with NIR window.  Honestly, for any near term activity, I would suggest to keep with the DLP650LNIR device and EVM, especially for this very high refresh rates at 24KHz.  For the .55 auto chip in current form, there are several new technology points that would need to be developed / qualified, so we do not have a clear plan.  Please note there were several design points on the auto chip to achieve the long life and high operating range needed for auto that were never developed / tested that enable the very high refresh rates.  Those changes would need to be revisited.  With that said, if the main benefit that you need is just the optical design compactness, then depending on the optics and f/# the design and folding scheme can be quite similar between the two chips.  I would also add that the 10.8um mirror will have a higher diffraction efficiency for NIR than 7.6um mirror.

  • 0 in reply to Jason Thompson
    TI__Intellectual 2325 points

    Please let us know if you have further questions or suggestions on this topic.

  • 0 in reply to Jason Thompson
    Prodigy 45 points

    Hi Jason

      Thanks for confirming. Just curious about the spec of this chip: so the 10kHz refresh rate means the 1-bit pattern rate? Or it actually stands for 8-bit or some other color patterns? And the circuit design of this chip is completely different from other DMD chips, or it's more or less similar so that loading and resetting still follow the same logic, and one could do something like random row accessing (I guess definitely not for the current evaluation board, but maybe in some future evaluation board?)

    Thanks

      Yujie

  • +1 in reply to Yujie Shen
    TI__Intellectual 2325 points

    Hi Yujie,

    First, the 10Khz is a single 1-bit pattern.  However, the DLPC230 controller does not really have features to make this available.   This 10KHz is more of a comment about fundamental speed at the DMD, but the system itself is only designed to work in "video" mode such as 8 bit grayscale.

    This DMD is fundamentally different the way in which the mirrors are constructed, switched, and controlled.  This is done specifically to meet long life and extreme temperature conditions needed for the automotive application.  Therefore, as designed / tested / built, this device could not achieve high refresh rates without additional R&D to prove out the methods that are used in other DMD chips.  With that that said, we will take this input and consider for future releases.

  • 0 in reply to Jason Thompson
    Prodigy 45 points

    Got it. Thanks Jason! I'll keep an eye on the future development then.

  • 0 in reply to Fizix
    Prodigy 45 points

    Hi Fizix

      Sorry to bother again. I see that the auto DMD's are in a completely different line and may not be feasible for SLM application at this point. So I guess we'll stick with the existing chipset. Just a few more things to confirm regarding the 9000 light rafter and also want to inquire about the 17-degree 5.4um chipset:

    1. So the DLPC900 could not do random row accessing, and the maximum number of 1-bit patterns that could be held in pre-stored or pattern on the fly mode is only a few hundreds, right?

    2. Another thing I read in the DLPC900 manual is that if the pattern is triggered, there has to be a dark frame between this one and the previous one. Could this be avoided through software?

    3. I recently noticed that we might also be able to use the DLP550YX or DLP670S chips, which when landed has the tilt direction along their rows or columns (please correct me if I am wrong). But TI seems to offer only DLPC900 as their controller. Is there a way to control them to have random row accessing, and maybe more memories to store more patterns? I visited some third party vendors (vialux or dli) and they don't even seem to support these chips...

    Thanks,

      Yujie

  • 0 in reply to Yujie Shen
    TI__Mastermind 45415 points

    Hello Yujie,

    You asked:

    1. So the DLPC900 could not do random row accessing, and the maximum number of 1-bit patterns that could be held in pre-stored or pattern on the fly mode is only a few hundreds, right?

    This is correct that random row addressing is not available in this chipset.  The controller DDR memory can only hold 400 1-bit patterns.  The flash can hold more, but again it would require stopping the display briefly and loading more.  These can be in flash which will load very quickly, but there would be a brief stop.

    2. Another thing I read in the DLPC900 manual is that if the pattern is triggered, there has to be a dark frame between this one and the previous one. Could this be avoided through software?

    Could you point me to the part in the manual you are referring to, so that I can be sure that this is correct?

    3. I recently noticed that we might also be able to use the DLP550YX or DLP670S chips, which when landed has the tilt direction along their rows or columns (please correct me if I am wrong). But TI seems to offer only DLPC900 as their controller. Is there a way to control them to have random row accessing, and maybe more memories to store more patterns? I visited some third party vendors (vialux or dli) and they don't even seem to support these chips...

    At this time the DLPC900 is the only controller that we offer for these two chips.  They are relatively new additions, so you may want to contact them to see if they are working on a product offering for them.

     Fizix

  • 0 in reply to Fizix
    Prodigy 45 points

    Hi Fizix

      Thanks for the reply. Just a few more questions following your response:

    • This is correct that random row addressing is not available in this chipset. The controller DDR memory can only hold 400 1-bit patterns. The flash can hold more, but again it would require stopping the display briefly and loading more. These can be in flash which will load very quickly, but there would be a brief stop.

         So how long would this stop time be for DLPC900 to load another 400 patterns into the DRAM? And for the current DLPCRC900EVM connecting to DLPCR50XEVM, say if I only need to update 6 blocks (BTW DLP500YX has 12 blocks, am I right?), in total how many 1-bit patterns can I put in as the pre-stored patterns?

    • Could you point me to the part in the manual you are referring to, so that I can be sure that this is correct?

       I was reading the Dual DLPC900 EVM user guide and saw section 3.6.4.1. But after re-reading it again I guess the blank was deliberately left there in the example. So if I run a series of patterns with no dark time and with trigger input, the previous pattern would just remain till the trigger signal comes, right?

  • 0 in reply to Yujie Shen
    TI__Expert 3820 points

    Hi Yujie,

    Fizix is out of office for the upcoming week, so I will be doing my best to answer some of your questions in his stead.

    1. So the DLPC900 could not do random row accessing, and the maximum number of 1-bit patterns that could be held in pre-stored or pattern on the fly mode is only a few hundreds, right?
    |
    The DLPC900/DLP9000 can only access one contiguous block of patterns, and the maximum number of 1-bit binary patterns that can be held in pattern-on the fly mode is 400 due to the controller design. You may also store 400 patterns in pre-stored pattern mode and switch between the two modes after stopping the first sequence of patterns and then loading and starting the next sequence.

    2. Another thing I read in the DLPC900 manual is that if the pattern is triggered, there has to be a dark frame between this one and the previous one. Could this be avoided through software?
    |
    I will talk to my team about this. I am sorry for the delay.

    3. I recently noticed that we might also be able to use the DLP550YX or DLP670S chips, which when landed has the tilt direction along their rows or columns (please correct me if I am wrong). But TI seems to offer only DLPC900 as their controller. Is there a way to control them to have random row accessing, and maybe more memories to store more patterns? I visited some third party vendors (vialux or dli) and they don't even seem to support these chips...
    |
    I am sorry, as Fizix has stated above, the DLPC900 only comprehends "global" resets. This means that a user-chosen block cannot be reset individually. Application note DLPA008B, Section 3 addresses the different DMD operations if you have not had a chance to look there yet.

    Quoting Fizix again, the newer EVM spins (when they become available) will have larger flash memory, enabling you to store more patterns inside pre-stored pattern mode.

    Thank you for addressing your concerns. We will try to get you more detailed answers within the upcoming week!



    Regards,
    Michael Ly

  • 0 in reply to Michael Ly
    Prodigy 45 points

    Hi Michael

      Thanks for your help. Actually could you also address the other questions I posted following Fizix's previous reply?

    "So how long would this stop time be for DLPC900 to load another 400 patterns from the flash memory into the DRAM? And for the current DLPCRC900EVM connecting to DLPCR50XEVM, say if I only need to update 6 blocks (BTW DLP500YX has 12 blocks, am I right?), in total how many 1-bit patterns can I put in as the pre-stored patterns?

    I was reading the Dual DLPC900 EVM user guide and saw section 3.6.4.1. But after re-reading it again I guess the blank was deliberately left there in the example. So if I run a series of patterns with no dark time and with trigger input, the previous pattern would just remain till the trigger signal comes, right?"

      Also I am curious when would the new generation of EVM boards become available?

    Thanks,

      Yujie

  • 0 in reply to Michael Ly
    Prodigy 45 points

    Hi Michael

      In addition to the question above, there's another thing: I talked to Vialux representatives and they said their V-650LNIR module (for DLP650LNIR control) could only select continuous blocks as AOI (no partitioning). I thought the controller for this chip could do random row accessing, right? Just want to confirm if it is possible to select segmented are as AOI (i.e. only 8 rows in a block)? Or maybe it's just vialux not implementing this function?

    Thanks,

    Yujie

  • 0 in reply to Yujie Shen
    TI__Mastermind 45415 points

    Hello again Yujie,

    The DLPC410 / DLP650LNIR chipset does support random row addressing.  I agree with you that it sounds like they did not implement this functionality in their module.  Just send them a message asking them to confirm since this is their product.  They should be able to answer.

    Fizix

  • 0 in reply to Fizix
    Prodigy 45 points

    Hi Fizix

      Thanks for confirming. Yeah I double-checked with vialux and unfortunately they could only update AOI in continuous rows.

      Could you also comment on the pattern transfer speed from flash to RAM in DLPC900 EVM board? So the RAM in the chip could hold 400 1bit patterns, right? Then if I want to transfer another new 400 patterns from flash to RAM how long would it take? Is it also possible to update the flash memory while the DMD is running with the patterns in the RAM?

      Also do you have an expectation when would the new generation of EVM modules be released?

    Thanks,

      Yujie

  • 0 in reply to Yujie Shen
    TI__Mastermind 45415 points

    Yujie,

    I will have to check on the actual load time for 400 patterns to load from flash.  

    It is not possible to update flash while the controller is running patterns in RAM.  These are exclusive operations.

    We are hoping to have next generation EVM controller modules near the end of this year, but there are no guarantees.

    Fizix

  • 0 in reply to Fizix
    TI__Mastermind 45415 points

    Yujie,

    I do not have an exact answer for the time, but it should generally be less than two seconds.  The patterns can have different level of compression in the Flash memory, so that the time will depend on the decompression into the controller's DDR memory.

    Fizix