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Question about data bus operation

Prince Ma
Prodigy 65 points

Dear Mr/Ms,
   I was trying to write a small program for testing with DLP@Discovery 4000 Kit. I want to display an image which is half white and half black. This means the 32-bit data bus will be writen all 0 for the first 8 clocks(16edges) and all 1 for the last 8 clocks(16 edges) in a row cycle. For a simulation it is as I have designed,but when I finished configuration, there is a problem.On the right half which should be "1" state, there are two thin straight lines ,quite obvious. Well, I can not find where the problem is. How could this happen? What do we need to care when we write the data bus ? Thank you for your attention.

  • 0
    TI__Intellectual 2265 points

    Dear Prince Ma,

    It is nice to hear your interest in learning more about the Discovery 4000 Kit. You might want to check your input data timing in relation to the dvalid signal. To see the exact timing requiremnts, please see the Discovery 4000 Data Sheet. If you you have any more technical questions, a good resource will be one of the Value Added Resellers (VARs) that can be found on the www.dlpdiscovery.com website.