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DLPC3433: Some flexibility on Layout suggestion

Wladimir De la Cadena
Prodigy 220 points
Part Number: DLPC3433

Hi,

I am routing the High speed signals of the DLPC3433, and trying to follow the layout the recommendations of the datasheet and reference design as much as possible. However, it has been difficult to find a manufacturer capable to fulfill the min track/width (2.3 mils) as in the reference layout. So, my question is whether any of the following suggestions (taken from the datasheet) are flexible to some extend:

  1. "The number of vias on DMD_HS signals should be minimized and should not exceed two" -> Could I use stacked vias (they count as 2 or 1?) and then have in total four vias in one signal?
  2. "Differential signals: Individual differential pairs can be routed on different layers,but the signals of a given pair should not change layers" -> Could I fanout using vias only on the _N signal and the P_ on other layer? This fanout would not exceed 2 mm.

I there is other flexibility on the rules or additional documentation where I can find more information, let me know

Wladimir

  • 0
    TI__Mastermind 28005 points

    Wladimir,

    For starters, have you checked the EVM reference design layouts available on TI.com as a reference? See https://www.ti.com/tool/TIDA-01571 and check for the "CAD Files".

    In terms of the flexibility of the layout rules, I'll investigate and give some further feedback in the next few days.

    Regards,

    Philippe Dollo

  • 0 in reply to Philippe Dollo
    Prodigy 220 points

    Yes, indeed that reference layout contains characteristics difficult to achieve by manufacturers. Therefore I tried to follow the recommendations of the data sheet ,in which I want to know how flexible they are. I hope you can give some insights on that. Thanks

  • 0 in reply to Wladimir De la Cadena
    TI__Mastermind 28005 points

    Wladimir,

    No problem. Will give you more detailed feedback within the next few days. Thanks for your patience.

    Regards,

    Philippe Dollo

  • 0 in reply to Philippe Dollo
    TI__Mastermind 28005 points

    Wladimir,

    Still working this issue. Thanks for your patience. Will update you again within a few days.

    Regards,

    Philippe Dollo

  • 0 in reply to Philippe Dollo
    TI__Mastermind 28005 points

    Wladimir,

    Some feedback from me on the above:

    1.     "The number of vias on DMD_HS signals should be minimized and should not exceed two" -> Could I use stacked vias (they count as 2 or 1?) and then have in total four vias in one signal?

    [TI] That’s okay.

    2.     "Differential signals: Individual differential pairs can be routed on different layers,but the signals of a given pair should not change layers" -> Could I fanout using vias only on the _N signal and the P_ on other layer? This fanout would not exceed 2 mm.

    [TI] It is recommended that you do not do this. It is advisable to keep the signals of a given pair on the same layer all the time. It is okay to route other pairs on a different layer.

    3.     I there is other flexibility on the rules or additional documentation where I can find more information, let me know

    [TI] We recommend that you look to our DLPCDLCR3010EVM-G2 reference design. This EVM uses the DLPC3433 and we have the layout files on TI.com. I posted a link to this reference design earlier in the thread

    I hope this helps.

    Regards,

    Philippe Dollo