Part Number: DLPC910
The connection between DLPC910 and DLPR910 is referred to TI DLPR910 datasheet. Now, the ECP2_FINISHED signal cann't go high , which means the program cann't be loaded.
The difference with datasheet is that the DLPC910's 50MHz clock is not driven by crystal. The FPGA supplys the 50MHz clock. Therefor, when the DLPC910 load the program, the 50MHz clock is not ready.
Does this difference matters?
And how to deal with the ECP2_FINISHED signal cann't go high ?
The APPS_FPGA or your front end should hold the DLPC900 in reset until it is up and sending training patterns. If it does not, it will not finish initialization correctly.
It is very much like the DLPC410 in this. If you have a D4100 EVM you will notice that the DLPC410 indicator starts red then briefly turns green then red and finally green. This is because once the APPS_FPGA starts running, the first thing it does is reset the DLPC410.
The DLPC910 requires this same sequence to initialize correctly. Since you are feeding the DLPC910 from the FPGA rather than crystal, you may need to add a delay after the FPGA starts sending the 50 MHz clock to the DLPC910 before pulling the DLPC910 into reset.
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In reply to Fizix:
Thanks for your answer. The DLPC910's reset is also supplied by FPGA, so before FPGA loads it's program, the 50MHz and reset signal are not ready.
Therefore, I try to reset the DLPC910 manually after the FPGA program is loaded, and at this situation, the 50MHz clock is ready. However, ECP2_FINISHED signal is still low.
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