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CC678 SRIO problem

Nick Zhang~
Intellectual 260 points


Dear all:
     I am working to send data from C6678 to the Xilinx's FPGA(Virtex6) in my own board.The SRIO is configured as 4x3.125G.
    

    There are two C6678s and one Virtex6 in the board, they are connected through the 4X SRIO. I can send data from FPGA to DSP or DSP to FPGA, and the data is all correct. But we meet a very strange problem.
    I send 1600 bytes from DSP to FPGA. In normal state, when i writed the LSU regs such as DestID, RapidIO address, DSP local address, Byte_count, DSP will send the 1600 bytes as 7 packets, FPGA should receive the 7 packets as well. The chipscope printscreen is below.

    

    We use the same functions(FPGA and DSP), Sometimes, FPGA receive the 7 packets unsequentially. The chipscope printscreen is below. This is not a normal state. But i don't konw where is wrong. SWRITE or NWRITE was tested. Sometimes correct, Sometimes wrong. we check the FPGA, we find that FPGA's and DSP's SRIO Link changed to 1X. If i configure the DSP in 4X mode, it can change to 1X???

    

    Another question, the table is right?

    Thank  you all!!!!

  • 0 in reply to Nick Zhang~
    TI__Intellectual 2415 points

    Hi Zhang,

    Yes. It is possible for a 4x link to downgrade to 1x link. This can happen, whenever one or more of the 4 lanes (in 4x mode) encounter lot of bit errors and lose lane sync status. Please, check the quality of the connection between C6678 and FPGA. Even if the link changes from 4x to 1x, I still don't understand the reason for out of order reception of SRIO packets. For any fixed SRIO priority and a point to point DSP to FPGA SRIO link, all SRIO packets should arrive in the same order as they were sent out.

    Do you see any SRIO physical or logical layer errors on the DSP or FPGA side?

    The PLL MPY settings shown in table 2-7 are correct. The following is the expression for calculating the MPY for a required line rate @ a particular RIO ref clock:

    RIO ref clock = (LINERATE * RATESCALE) / MPY

    RATESCALE = 0.25 (full rate), 0.5 (Half rate), 1 (Quarter rate) and 2 (Eighth)

    I hope this helps.

  • 0 in reply to Karthik Ramana Sankar
    Intellectual 260 points

    Thank you for your reply. I will check them.